Process controls for improved wafer uniformity using integrated or standalone metrology
AssigneeLam Research Corporation
InventorsGowri P. Kota, Jorge Luque
Life of this patent
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Abstract
A method and apparatus is provided for measuring multiple locations on a wafer for controlling a subsequent semiconductor processing step to achieve greater dimensional uniformity across that wafer. The method and apparatus maps a dimension of a feature at multiple locations to create a dimension map, transforms the dimension map into a processing parameter map, and uses the processing parameter map to tailor the subsequent processing step to that specific wafer. The wafer can also be measured after the processing to compare an actual outcome with the targeted outcome, and the difference can be used to refine the transformation from a dimension map to a processing parameter map for a subsequent wafer.
Claims34
A method for controlling processing of a wafer comprising:
- determining a dimension map of a plurality of features on the wafer, the plurality of features including a plurality of test patterns, the test patterns including a sufficient number of evenly spaced repeating features in a measurement area, the evenly spaced repeating features having a dimension with a known correlation to a dimension of a feature of interest;
- determining a processing parameter map from the dimension map;
- and
- processing the wafer according to the processing parameter map.
A method for controlling processing of a wafer comprising:
- determining a dimension map of a plurality of features on the wafer including measuring the plurality of features by spectroscopic ellipsometry;
- determining a processing parameter map from the dimension map;
- and
- processing the wafer according to the processing parameter map.
A method for controlling processing of a wafer comprising:
- determining a dimension map of a plurality of features on the wafer including measuring the plurality of features with a reflectometer-based CD measurement technique;
- determining a processing parameter map from the dimension map;
- and
- processing the wafer according to the processing parameter map.
A method for controlling processing of a wafer comprising:
- determining, with a metrology tool that is integrated with a processing chamber, a dimension map of a plurality of features on the wafer;
- determining a processing parameter map from the dimension map;
- and
- processing the wafer in the processing chamber according to the processing parameter map.
A method for controlling processing of a wafer comprising:
- determining, with a metrology tool that stands alone from a processing chamber, a dimension map of a plurality of features on the wafer;
- determining a processing parameter map from the dimension map;
- and
- processing the wafer in the processing chamber according to the processing parameter map.
A method for controlling processing of a wafer comprising:
- determining a dimension map of a plurality of features on the wafer;
- determining a processing parameter map from the dimension map, the processing parameter map establishing a temperature for a temperature tunable chuck;
- and
- processing the wafer according to the processing parameter map.
A method for controlling processing of a wafer comprising:
- determining a dimension map of a plurality of features on the wafer;
- determining a processing parameter map from the dimension map, the processing parameter map establishing a temperature range for a temperature tunable chuck;
- and
- processing the wafer according to the processing parameter map.
A method for controlling wafer processing comprising:
- determining a dimension map of a plurality of features on the wafer;
- determining a processing parameter map from the dimension map;
- processing the wafer according to the processing parameter map to create a post-processing feature on the wafer;
- determining a dimension of the post-processing feature;
- determining a figure of merit from the dimension of the post-processing feature;
- and
- determining a processing parameter for a subsequent wafer according to the figure of merit.
A wafer processing system comprising:
- means for determining a dimension map of a plurality of features on the wafer, the means including a metrology tool;
- means for determining a processing parameter map from the dimension map;
- and
- means for processing the wafer according to the processing parameter map.
A wafer processing system comprising:
- means for determining a dimension map of a plurality of features on the wafer;
- means for determining a processing parameter map from the dimension map;
- and
- means for processing the wafer according to the processing parameter map, the means including a semiconductor processing system.
A wafer processing system comprising:
- means for determining a dimension map of a plurality of features on the wafer;
- means for determining a processing parameter map from the dimension map;
- means for processing the wafer according to the processing parameter map to create a post-processing feature on the wafer;
- means for determining a dimension of the post-processing feature;
- means for determining a figure of merit from the dimension of the post-processing feature;
- and
- means for determining a processing parameter for a subsequent wafer according to the figure of merit.
Dependencies are inferred from the claim text.