Phase shifting lithographic process
AssigneeUnited Microelectronics Corp.
InventorBenjamin Szu-Min Lin
Life of this patent
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Abstract
A dual phase shifting mask (PSM)/double exposure lithographic process for manufacturing a shrunk semiconductor device. A semiconductor wafer having a photoresist layer coated thereon is provided. A first phase shift mask is disposed over the semiconductor wafer and implementing a first exposure process to expose the photoresist layer to light transmitted through the first phase shift mask so as to form a latent pattern comprising a peripheral unexposed line pattern in the photoresist layer. The first phase shift mask is then replaced with a second phase shift mask and implementing a second exposure process to expose the photoresist layer to light transmitted through the second phase shift mask so as to remove the peripheral unexposed line pattern.
Claims10
A phase shifting lithographic process capable of creating a shrunk fine line pattern on a photoresist layer coated on a semiconductor wafer, the shrunk fine line pattern comprising a first fine line image and a second fine line image connected to the first fine line image, the phase shifting lithographic process comprising:
- providing a first phase shift mask comprising thereon a first phase shift clear area, a second phase shift clear area situated adjacent to the first phase shift clear area, a first control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, and a first opaque area connected to the first control chrome line section;
- implementing a first exposure process to expose the photoresist layer to light transmitted from clear areas of the first phase shift mask so as to form the first fine line image corresponding to the first control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, a first unexposed area connected to the first fine line image, and a peripheral unexposed line pattern;
- providing a second phase shift mask comprising thereon a third phase shift clear area, a fourth phase shift clear area situated adjacent to the third phase shift clear area, a second control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area, and a second opaque area connected to the second control chrome line section for shielding the first fine line image on the photoresist layer;
- and
- implementing a second exposure process to expose the photoresist layer to light transmitted from clear areas of the second phase shift mask so as to form the second fine line image corresponding to the second control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area.
A double exposure lithographic process for manufacturing a shrunk semiconductor device, comprising:
- providing a semiconductor wafer having a photoresist layer coated thereon;
- providing a first phase shift mask disposed over the semiconductor wafer and implementing a first exposure process to expose the photoresist layer to light transmitted through the first phase shift mask so as to form a latent pattern comprising a peripheral unexposed line pattern in the photoresist layer;
- and
- replacing the first phase shift mask with a second phase shift mask and implementing a second exposure process to expose the photoresist layer to light transmitted through the second phase shift mask so as to remove the peripheral unexposed line pattern.
Dependencies are inferred from the claim text.