Frequency divider and related method of design

A non-integer frequency divider for dividing an original clock to form a target clock, the frequency of the target clock being equal to the frequency of the original clock divided by (2n+1)/2, n being a positive integer equal to or greater than 1, the non-integer frequency divider comprising:

• a phase shifter for generating a first clock and a second clock according to the original clock;
• a first dividing circuit receiving the first clock and generating a first target clock in cooperation with a first front set circuit, a first middle set circuit and a first rear set circuit connected serially in sequence inside, wherein the first front set circuit comprises a first clock generator and a first logic gate, the first middle set circuit comprises a second clock generator, k1 serially connected first sets of clock generators in which k1≧0, and n−k1−1 serially connected second sets of clock generators in which n−k1−1≧0, the k1 serially connected first sets of clock generators being initially set to different values than the n−k1−1 serially connected second sets of clock generators, and the first rear set circuit comprises a third clock generator and a second logic gate;
• a second dividing circuit receiving the second clock and generating a second target clock in cooperation with a second front set circuit, a second middle set circuit and a second rear set circuit connected serially in sequence inside, wherein the second front set circuit comprises a fourth clock generator and a third logic gate, the second middle set circuit comprises a fifth clock generator, k2 serially connected third sets of clock generators in which k2≧0, and n−k2−1 serially connected fourth sets of clock generators in which n−k2−1≧0, the k2 serially connected third sets of clock generators being initially set to different values than the n−k2−1 serially connected fourth sets of clock generators, and the second rear set circuit comprises a sixth clock generator and a fourth logic gate;
• and
• a synthesizing circuit outputting the target clock according to the first target clock and the second target clock.

A frequency divider dividing an original clock into a target clock, the frequency of the target clock being equal to the frequency of the original clock divided by M, M being a positive odd integer equal to or greater than 3, the frequency divider comprising:

• a front set circuit comprising:
• a first clock generator with a clock input end connected to a trigger clock having a frequency the same as that of the original clock and a trigger phase;
• and
• a first logic gate with a first input end connected to an output end of the first clock generator, and a second input end connected to a signal input end of the first clock generator;
• a middle set circuit comprising:
• a second clock generator with a clock input end connected to the trigger clock, and a signal input end connected to an output end of the first logic gate in the front set circuit;
• and
• a rear set circuit comprising:
• a third clock generator with a clock input end connected to the trigger clock, and a signal input end connected to an output end of the second clock generator in the middle set circuit;
• and
• a second logic gate with a first input end connected to an output end of the third clock generator in the rear set circuit, a second input end connected to the output end of the second clock generator in the middle set circuit, and an output end for outputting the target clock.

A method for designing a frequency divider to divide an original clock to form a target clock, the method comprising:

• phase shifting the original clock to generate a first clock and a second clock according to the original clock, the first clock and the second clock being out of phase with each other and each having the same frequency as the original clock;
• dividing the frequency of each of the first clock and the second clock by a factor of M to respectively generate first and second divided clocks, M being a positive odd integer equal to or greater than 3;
• and
• performing an XOR logic operation on the first and second divided clocks to generate the target clock with a frequency that is twice the frequency of the first and second divided clocks.