Versatile system for controlling semiconductor topography
AssigneeTexas Instruments Incorporated
InventorsNital S. Patel, Rajesh Tiwari
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AssigneeTexas Instruments Incorporated
InventorsNital S. Patel, Rajesh Tiwari
Estimating the term…
The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator. A processing control function (210) receives the processing target, and alters the copper overpolish or barrier polish responsive to the processing target.
A system for controlling post-processing topology of semiconductor wafers, the system comprising:
A method for controlling post-processing topology of semiconductor wafers that utilize copper metallization, the method comprising the steps of:
A system for selectively controlling post-CMP dishing effects occurring in semiconductor wafers utilizing copper metallization, the system comprising:
Dependencies are inferred from the claim text.