A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit;
- said first memory unit having;
- (A-1) a first bit line,
- (B-1) first transistors for selection which are N in number (N>2),
- (C-1) first sub-memory units which are N in number and each of which is composed of memory cells which are M in number (M>2), and
- (D-1) plate lines which are M in number and each of which is shared with each memory cell constituting each of the first sub-memory units which are N in number, between or among the first sub-memory units which are N in number, and
- said second memory unit having;
- (A-2) a second bit line,
- (B-2) second transistors for selection which are N in number,
- (C-2) second sub-memory units which are N in number and each of which is composed of memory cells which are M in number, and
- (D-2) the plate lines which are M in number, each of which is shared with each memory cell constituting each of the second sub-memory units which are N in number, between or among the second sub-memory units which are N in number, and which are shared with the plate lines which constitute said first memory unit and are M in number,
- wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . N) and the second sub-memory unit of the n-th layer are formed on the same insulating layer,
- the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′-1)-th layer and the second sub-memory unit of the (n′-1)-th layer through the insulating layer,
- each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
- in the first memory unit, the first electrodes of the memory cells constituting the first sub-memory unit of the n-th layer are in common with the first sub-memory unit of the n-th layer, said common first electrode is connected to the first bit line through the n-th-place first transistor for selection, and the second electrode of the memory cell in an m-th-place (m=1, 2 . . . M) is connected to the common plate line in the m-th-place,
- in the second memory unit, the first electrodes of the memory cells constituting the second sub-memory unit of the n-th layer are in common with the second sub-memory unit of the n-th layer, said common first electrode is connected to the second bit line through the n-th-place second transistor for selection, and the second electrode of the memory cell in the m-th-place is connected to the common plate line in the m-th-place,
- the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the same thermal history with regard to their production processes,
- the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer,
- the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and the memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store data of 1 bit each,
- a reference potential having an n-th potential is provided to the second bit line when data stored in the memory cell constituting the first sub-memory unit of the n-th layer in the first memory unit is read out,
- a reference potential having an n-th potential is provided to the first bit line when data stored in the memory cell constituting the second sub-memory unit of the n-th layer in the second memory unit is read out, and
- the n-th potential differs from the k-th potential (k≠n), and further wherein reference capacitors which are N in number are further provided and the reference capacitor in an n-th-place provides a reference potential having an n-th potential;
- and
- wherein at least one reference capacitor is an MOS capacitor.