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US 7,009,277 B2Granted
Semiconductor device with improved radiation property
AssigneeRenesas Technology Corp.
InventorYasuo Yamaguchi
Life of this patent
Estimating the term…
Abstract
To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).
Claims20
A semiconductor device comprising:
- a semiconductor substrate having a principal plane in which an insulation film is selectively formed;
- an insulating layer formed on said principal plane;
- a heat generating layer embedded in said insulation layer and opposing to said principal plane with a part of said insulation layer interposed between said heat generating layer and said principal plane;
- a first wiring layer disposed on said insulation layer;
- a second wiring layer disposed on said insulation layer;
- a first plug embedded in said insulation layer, a lower end of said first plug being connected to one end of said heat generating layer and an upper end of said first plug being connected to said first wiring layer;
- a second plug embedded in said insulation layer, a lower end of said second plug being connected to other end of said heat generating layer and an upper end of said second plug being connected to said second wiring layer;
- and
- a third plug embedded in said insulation layer, an upper end of said third plug being connected to said first wiring layer or said first plug and a lower end of said third plug reaching said insulation film of said principal plane.
6 more elements
A semiconductor device comprising:
- a substrate having a principal plane;
- an insulation layer formed on said principal plane;
- a heat generating layer embedded in said insulation layer and opposing to said principal plane with a part of said insulation layer interposed between said heat generating layer and said principal plane;
- a first wiring layer disposed on said insulation layer, which is a wiring layer for transmitting stable potential, a width of said wiring layer being elongated so as to be larger than or equal to a width based on a design rule in a region including a portion positioned above one end of said heat generating layer;
- a second wiring layer disposed on said insulation layer;
- a first plug embedded in said insulation layer, a lower end of said first plug being connected to said one end of said heat generating layer, an upper end of said first plug being connected to said portion of said first wiring layer, said first plug having a cross sectional shape along said principal plane of a rectangle, short sides of said rectangle being parallel to a main direction connecting said one end and other end of said heat generating layer and long sides of said rectangle being parallel to a direction perpendicular to said main direction;
- and
- a second plug embedded in said insulation layer, a lower end of said second plug being connected to said other end of said heat generating layer and an upper end of said second plug being connected to said second wiring layer.
5 more elements
A semiconductor device comprising:
- a substrate having a principal plane;
- an insulation layer formed on said principal plane;
- a heat generating layer embedded in said insulation layer and opposing to said principal plane with a part of said insulation layer interposed between said heat generating layer and said principal plane, said heat generating layer having a channel region and a pair of source and drain regions at one end and other end sandwiching said channel region;
- a gate electrode embedded in said insulation layer, opposing to said channel region with another part of said insulation layer interposed between said gate electrode and said channel region;
- a first wiring layer disposed on said insulation layer, which is a wiring layer for transmitting stable potential, a width of said wiring layer being elongated so as to be larger than or equal to a width based on a design rule in a region including a portion positioned above one of said pair of source and drain regions;
- a second wiring layer disposed on said insulation layer;
- a first plug embedded in said insulation layer, a lower end of said first plug being connected to said one of the pair of source and drain regions and an upper end of said first plug being connected to said portion of said first wiring layer;
- a second plug embedded in said insulation layer, a lower end of said second plug being connected to other of said pair of source and drain regions and an upper end of said second plug being connected to said second wiring layer;
- an electrode material layer embedded in said insulation layer, positioned directly under said region of said first wiring layer, made of the same material and having the same thickness as said gate electrode, isolated from said gate electrode;
- and
- a connection plug embedded in said insulation layer, an upper end of said connection plug being connected to said region of said first wiring layer and a lower end of said connection plug being connected to said electrode material layer.
8 more elements
Dependencies are inferred from the claim text.