Semiconductor device and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorHideaki Nii
Life of this patent
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Abstract
A method of manufacturing a semiconductor device is provided. The method includes providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type. An opening is formed penetrating the device isolation region and the embedded insulation layer and reaching the semiconductor substrate. A polysilicon is deposited on the SOI substrate and within the opening and providing a gate electrode and a substrate electrode of the MIS type field-effect transistor by executing the patterning thereon; and implanting impurities into the gate electrode and the substrate electrode.
Claims8
A method of manufacturing a semiconductor device, comprising:
- providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation layer on a semiconductor substrate of a first conductivity type;
- forming an opening penetrating said device isolation region and said embedded insulation layer and reaching said semiconductor substrate;
- depositing polysilicon on said SOI substrate and within said opening and providing a gate electrode and a substrate electrode of said MIS type field-effect transistor by executing the patterning thereon;
- and
- implanting impurities into said gate electrode and said substrate electrode,
- wherein the impurity is implanted into said substrate electrode in the same step of doping into a diffused layer of said MIS type field-effect transistor.
A method of manufacturing a semiconductor device, comprising
- providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation layer on a semiconductor substrate of a first conductivity type;
- forming an opening penetrating said device isolation region and said embedded insulation layer and reaching said semiconductor substrate;
- depositing polysilicon on said SOI substrate and within said opening and providing a gate electrode and a substrate electrode of said MIS type field-effect transistor by executing the patterning thereon;
- and
- implanting impurities into said gate electrode and said substrate electrode,
- providing, after forming said opening, a second conductivity type impurity diffused layer by implanting a second conductivity type impurity into the surface of said semiconductor substrate via said opening.
A method of manufacturing a semiconductor device, comprising:
- providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation layer on a semiconductor substrate of a first conductivity type;
- providing a first polysilicon layer on the entire surface;
- forming an opening penetrating said first polysilicon layer, said device isolation region and said embedded insulation layer and reaching said semiconductor substrate;
- providing a second polysilicon layer on the entire surface to cover said opening;
- providing a substrate electrode by patterning said first and second polysilicon layers;
- and
- implanting an impurity into said substrate electrode.
Dependencies are inferred from the claim text.