Out of the box vertical transistor for eDRAM on SOI

#The present invention relates to electronic devices, and more particularly to vertical memory devices, such as eDRAM devices, formed within a silicon-on-insulator (SOI) substrate.

#Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size affects chip density, and cost, reducing cell area is one of the DRAM designer's primary goals.

#One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Trench capacitors can be formed by etching deep trenches in a silicon wafer and forming vertically orientated capacitors within each deep trench. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge. Each deep trench may have a depth on the order of 1 μm or greater. In order to further decrease the density of the device, the access transistor can also be positioned in a vertical orientation, as opposed to a planar orientation.

#FIG. 1 is an illustration of a cross-sectional view of one embodiment of the present memory array and support array regions formed within a silicon-on-insulator substrate, in which the memory array includes memory devices having an out-of-buried insulator upper strap and the support region includes logic devices.

#FIGS. 2–9 illustrate (through cross-sectional view) the process steps for producing the memory array depicted in FIG. 1.

#A memory array and support structure in SOI substrates, and method of forming the same, will now be discussed in greater detail by referring to the drawings that accompany the present application. In the accompanying drawings, like and corresponding parts are referred to by like reference numbers. Although the drawings show the presence of an array region containing only two memory devices and a support region containing only a single logic device, multiple memory devices and multiple logic devices are also within the scope of the present invention.

#The present memory array and support structure combines the high-drive current and high-density characteristics possible in a vertical memory device, with the superior logic devices formed on a silicon-on-insulators (SOI) substrate. The advantages of forming logic devices on SOI substrates include higher packing density, the reduction of latch-up effects, lower junction capacitance, suitability to low-voltage applications, and higher performance.

#Referring to FIG. 1, the SOI substrate 10 includes an upper Si-containing layer (SOI layer) 11, a buried insulating region 12, and a bulk silicon portion 13. The array region 4 comprises at least one trench 15, where each trench 15 may comprise a memory device. Each memory device comprises a capacitor 2 and an access transistor 3 separated by a trench top oxide 24.