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US 7,009,229 B1Granted
Electrostatic discharge protection device for integrated circuits
AssigneeLovoltech, Inc.
InventorsChong Ming Lin, Ho Yuan Yu
Life of this patent
Estimating the term…
Abstract
A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.
Claims18
A semiconductor device comprising:
- a dielectric layer formed on a surface of a semiconductor substrate, wherein said dielectric layer comprises a portion disposed above an n-type well;
- a first interface bonding pad formed on a surface of said dielectric layer, wherein said bonding pad comprises a portion disposed above said n-type well;
- a first enhancement mode junction field effect transistor (JFET) comprising a first threshold voltage formed in said n-type well and disposed beneath said interface bonding pad, said JFET comprising a gate coupled to said interface bonding pad, a drain coupled to said interface bonding pad, and a source coupled to said p-type semiconductor substrate wherein said drain and said source are electrically coupled to said first interface bonding pad;
- and
- a source contact formed in said n-type well.
2 more elements
A semiconductor device comprising:
- a dielectric layer formed on a surface of said semiconductor substrate, wherein said dielectric layer comprises a portion disposed above a p-type well;
- a first interface bonding pad formed on a surface of said dielectric layer, wherein said bonding pad comprises a portion disposed above said p-type well;
- a first enhancement mode junction field effect transistor (JFET) comprising first threshold voltage formed in said p-type well and disposed beneath said interface bonding pad, said JFET comprising a gate coupled to said interface bonding pad, a drain coupled to said interface bonding pad, and a source coupled to an n-type semiconductor substrate wherein said drain and said source are electrically coupled to said first interface bonding pad;
- and
- a source contact formed in said p-type well.
2 more elements
An integrated circuit comprising:
- a complementary well formed in the surface of a semiconductor substrate;
- a first vertical enhancement mode junction field effect transistor (JFET) formed in said complementary well, a source coupled to said semiconductor substrate, and a drain coupled to a gate, and a first threshold voltage;
- and
- a first interface bonding pad disposed above said JFET, wherein said first bonding pad is coupled to said gate and to said drain wherein said drain and said source are electrically coupled to said first interface bonding pad.
1 more element
Dependencies are inferred from the claim text.