US 7,008,844 B2 · Method of forming a gate of a non-volatile memory device

Abstract

A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.

Claims11

Dependent claims

A method of forming a gate in a non-volatile memory device comprising:

forming a tunnel dielectric layer on a semiconductor substrate;
forming a floating gate layer on the tunnel dielectric layer;
forming an intergate dielectric layer on the floating gate layer;
forming a control gate layer comprising an in-situ doped amorphous silicon layer on the intergate dielectric layer;
forming a metal silicide layer on the control gate layer;
crystallizing the amorphous silicon layer by annealing the control gate layer after forming the metal silicide layer;
and
patterning the control gate layer, the intergate dielectric layer, the floating gate layer, and the metal silicide layer.

5 more elements

Dependencies are inferred from the claim text.

Method of forming a gate of a non-volatile memory device

Life of this patent

Method of forming a gate of a non-volatile memory device

Life of this patent

Abstract

Claims11