Methods and apparatus for injecting an external clock into a circuit
AssigneeAeluros, Inc.
InventorArnold R. Feldman
Life of this patent
Estimating the term…
Abstract
A synchronous circuit implements a bypass mode for use in conjunction with an inductive-capacitive (“LC”) buffer. The LC buffer receives differential conventional clock signals, and generates buffered differential conventional clock signals. A synchronous circuit, such as a latch, includes at least two clock receivers. The conventional clock signal is input to the first clock receiver, such as a transistor, and an auxiliary clock is input to a second clock receiver. The conventional clock signal provides timing for the synchronous circuit under a normal mode of operation, and the auxiliary clock signal provides timing for the synchronous circuit under a test mode of operation at a frequency lower than the conventional clock signal.
Claims29
A circuit comprising:
- inductive-capacitive (“LC”) buffer for receiving a clock signal and for generating a first clock signal;
- and
- at least one synchronous circuit comprising first and second clock inputs, said first clock input for receiving said first clock signal, said first clock signal for providing timing for said synchronous circuit under a normal mode of operation, and said second clock input for receiving a second clock signal, said second clock signal for providing timing for said synchronous circuit under a test mode of operation, said second clock signal comprising a frequency lower than said first clock signal.
A circuit comprising:
- synchronous circuit comprising at least one input clock line for receiving a clock signal for said circuit;
- first clock receiver circuit for receiving a first clock signal and for providing timing to said circuit under normal mode of operation;
- and
- second clock receiver circuit, coupled to said clock signal line and coupled parallel to said first clock receiver circuit, for receiving a second clock signal and for providing timing to said circuit under a test mode of operation, said second clock signal comprising a frequency lower than said first clock signal.
A method for providing a test clock for a circuit, said method comprising the steps of:
- receiving a clock signal at an inductive-capacitive (“LC”) buffer;
- generating a first clock signal at said LC buffer;
- receiving said first clock signal at a first input of a synchronous circuit;
- receiving said first clock signal at a first input of a synchronous circuit;
- providing timing for said synchronous circuit under a normal mode of operation with said first clock signal;
- receiving a second clock signal at a second input of a synchronous circuit, said second input being parallel to said first input;
- and
- providing timing for said synchronous circuit under a test mode of operation with said second clock signal.
A circuit comprising:
- inductive-capacitive (“LC”) buffer for receiving a first clock signal and for buffering said first clock signal;
- buffer, coupled to said LC buffer, for receiving said first clock signal and a second clock signal, and for buffering, during a normal mode of operation, said first clock signal or for buffering said second clock signal during a bypass clock mode of operation;
- and
- synchronous circuit comprising an input clock line coupled to said buffer for receiving on said input clock line said first clock signal during said normal mode of operation and said second clock signal during said bypass clock of operation.
Dependencies are inferred from the claim text.