Dissection of edges with projection points in a fabrication layout for correcting proximity effects
AssigneeSynopsys, Inc.
InventorsChristophe Pierrat, Youping Zhang
Life of this patent
Estimating the term…
Loading patent…
AssigneeSynopsys, Inc.
InventorsChristophe Pierrat, Youping Zhang
Estimating the term…
Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point.
A method of correcting for proximity effects in a layout, the layout including a first layout for a trim mask and a second layout for a phase-shifting mask, the trim mask and the phase-shifting mask used to fabricate a wafer, the method comprising:
A method of correcting for proximity effects in a layout, the layout including a first layout for a trim mask and a second layout for a phase-shifting mask, the trim mask and the phase-shifting mask used to fabricate a wafer, the method comprising:
Dependencies are inferred from the claim text.