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US 7,002,842 B2Granted
Floating-body dynamic random access memory with purge line
AssigneeIntel Corporation
InventorsStephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien Lu, Vivek K. De
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Abstract
Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
Claims36
An apparatus comprising:
- a transistor to store data, wherein:
- a gate of the transistor is configured to receive a first control signal;
- a first channel interface of the transistor is configured to receive a data signal;
- and
- a second channel interface of the transistor is configured to receive a second control signal, the data being stored in the transistor by resetting a floating body of the transistor and then writing the data to the floating body, the floating body being reset when the second control signal assumes a first value, the first value being lower than a second value which the second control signal assumes when the data is written into the floating body, and wherein the first channel interface is a drain and the second channel interface is a source of the transistor.
2 more elements
A method comprising:
- resetting a floating body of the transistor with a first set of control signals overlapping in time;
- and
- selectively writing data to the floating body of the transistor with a second set of control signals and a data signal overlapping in time, the first set of control signals and the second set of control signals being received at a gate of the transistor and a source of the transistor, and the data signal is received at a drain of the transistor,
- the first set of control signals including a purge signal coupled to the source of the transistor, the purge signal having a first value lower than a second value which is coupled to the source when the data is selectively written to the floating body of the transistor.
1 more element
A system comprising:
- a die comprising a processor;
- and
- an off-die component in communication with the processor;
- wherein the processor comprises a transistor to store data, wherein:
- a gate of the transistor is configured to receive a first control signal;
- a first channel interface of the transistor is configured to receive a data signal;
- and
- a second channel interface of the transistor is configured to receive a second control signal, the data being stored in the transistor by resetting a floating body of the transistor and then writing the data to the floating body, the floating body being reset when the second control signal assumes a first value, the first value being lower than a second value which the second control signal assumes when the data is written into the floating body, and wherein the first channel interface is a drain and the second channel interface is a source of the transistor.
5 more elements
A memory cell, comprising:
- a transistor including:
- (a) a gate coupled to a word line,
- (b) a drain coupled to a bit line,
- (c) a source coupled to a purge line, and
- (d) a floating body between the source and drain,
- the purge line assuming a first value during a reset operation and a second value when data is stored in the floating body during a write operation, the first value being lower than the second value.
3 more elements
Dependencies are inferred from the claim text.