Back to results
US 7,002,253 B2Granted
Semiconductor device and design method thereof
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsAkihito Katsura, Hiroo Yamamoto
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsAkihito Katsura, Hiroo Yamamoto
Estimating the term…
It is an object of the present invention to achieve a semiconductor device capable of preventing circuit malfunctions caused by noise without decreasing an integration degree of the circuit by making a space between signal interconnections wider and inserting a shield or a shield layer between the signal interconnections. The semiconductor device has a multilayer interconnection structure wherein three or more interconnection layers are stacked on a silicon semiconductor substrate, and comprises: a first signal line which is formed with a (N−1)-th interconnection layer and comprises a latch circuit; a second signal line which is formed with a (N+1)-th interconnection layer and is arranged so as to cross the first signal line or partially overlap thereover; and a power supply interconnection serving as a shield interconnection which is formed with an N-th interconnection layer in a portion directly beneath the first signal line and the second signal line.
In a semiconductor device wherein a plurality of interconnection layers including a (N−1)-th (N is an integer equal to two or more) interconnection layer, and an N-th interconnection layer are stacked on a substrate from a lower layer to an upper layer in order, and insulating layers are provided between the substrate and the lowest interconnection layer, and between respective interconnection layers, respectively, the semiconductor device, comprising:
A semiconductor device, wherein semiconductor elements are formed on a substrate, the semiconductor device comprising:
Dependencies are inferred from the claim text.