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US 7,002,216 B2Granted
ESD performance using separate diode groups
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShao-Chang Huang
Life of this patent
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Abstract
Disclosed are architectures and method for semiconductor ESD protection using grouped diodes, with the diode groups being electrically separated by substrate resistance. The mixed diode/resistor groups are arranged to be in an off state under normal operating conditions and to discharge ESD current between power lines. The disclosed architectures and method protects circuits using different power supplies and/or voltage inputs.
Claims15
A series-diode circuit formed in an integrated circuit, comprising:
- a) a first diode having first and second terminals and formed in a first active region of a semiconductor substrate;
- b) a second diode having first and second terminals and formed in a second active region of the semiconductor substrate;
- c) a third diode having first and second terminals and formed in a third active region of the semiconductor substrate;
- d) a first electrical connection that electrically connects the second terminal of the first diode to the first terminal of the second diode;
- and
- e) a second electrical connection that electrically connects the second terminal of the second diode to the first terminal of the third diode;
- f) wherein the third active region comprising the third diode is physically separated from the first and second active regions sufficiently far to interpose substantial electrical resistance between the third active region and the first and second active regions.
4 more elements
An semiconductor device protection circuit comprising:
- a) a first input;
- b) a second input;
- c) a first pnp-transistor diode formed in a first n-well on a p-substrate, the first transistor diode having a first, emitter terminal formed at a p-type area electrically connected to the first input, a base formed by the first n-well adjacent to the p-type area, and a collector formed by the p-substrate adjacent to the first n-well, wherein the base is a second terminal;
- d) a second pnp-transistor diode formed in a second n-well on the p-substrate, the second transistor diode having an first, emitter terminal formed at a p-type area electrically connected to the second terminal of the first transistor diode, a base formed by the second n-well adjacent to the p-type area, and a collector formed by the p-substrate adjacent to the second n-well, wherein the base is a second terminal;
- e) a third pnp-transistor diode formed in a third n-well on the p-substrate, the third transistor diode having an first, emitter terminal formed at a p-type area electrically connected to the second terminal of the second transistor diode, a base formed by the third n-well adjacent to the p-type area, and a collector formed by the p-substrate adjacent to the third n-well, wherein the base is a second terminal and is connected to the second input and
- f) wherein the third n-well is physically separated from the first and second n-wells sufficiently far enough to interpose substantial electrical resistance between the third n-well and the first and second n-wells such that leakage current through the combination of the first, second, and third pnp-transistor diodes is substantially reduced.
3 more elements
Dependencies are inferred from the claim text.