Semiconductor memory with nonvolatile memory cell array and semiconductor device with nonvolatile memory cell array and logic device
AssigneeKabushiki Kaisha Toshiba
InventorsSeiichi Mori, Shigeru Atsumi
Life of this patent
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Abstract
A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.
Claims10
A semiconductor device at least having a nonvolatile memory at least having a memory cell array structure that comprises:
- active regions extending linearly in parallel with one another and containing impurity diffused source and drain regions;
- element isolation regions extending linearly and isolating the active regions from one another;
- gate electrodes orthogonally crossing the active regions and element isolation regions and each having a floating gate and a control gate laid one upon another;
- first conductors formed from a first metal wiring layer, the first conductors extending linearly in parallel with the gate electrodes and each connecting the source regions to one another between adjacent ones of the gate electrodes;
- and
- second conductors formed from a second metal wiring layer that is above the first metal wiring layer, the second conductors orthogonally crossing the gate electrodes and connected to the drain regions through contacts.
Dependencies are inferred from the claim text.