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US 7,002,200 B2Granted
Self-aligned structure with unique erasing gate in split gate flash
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChia-Ta Hsieh
Life of this patent
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Abstract
A split-gate flash memory device. The device includes a floating gate, a control gate, and an erase gate. The floating gate is overlying a substrate. The control gate is laterally adjacent to the floating gate and overlying the substrate. The erase gate is laterally adjacent to the floating gate and overlying the control gate, in which the erase gate is between a sidewall spacer and the floating gate.
Claims21
A split-gate flash memory device comprising:
- a floating gate overlying a substrate;
- a control gate overlying said substrate, comprising at least one sidewall laterally adjacent to said floating gate, and a top surface;
- and
- an erase gate laterally adjacent to said floating gate and overlying said top surface of said control gate wherein said erase gate is between a sidewall spacer and said floating gate.
1 more element
A split-gate flash memory device comprising:
- a floating gate overlying a substrate;
- a structural dielectric layer overlying the floating gate;
- a control gate laterally adjacent to the floating gate and overlying the substrate;
- a sidewall spacer overlying the control gate;
- an erase gate surrounded by an erase dielectric layer, overlying the control gate and between the sidewall spacer and the structural dielectric layer;
- a source region in the substrate adjacent to the floating gate;
- and
- a drain region in the substrate outside of the control gate.
5 more elements
A split-gate flash memory device comprising:
- a substrate having a source region and a drain region;
- a source plug disposed on the source region;
- a floating gate overlying the substrate adjacent to the source region and insulated from the substrate;
- a structural dielectric layer overlying the floating gate;
- a control gate laterally adjacent to the floating gate and overlying the substrate, wherein the control gate is insulated from the floating gate and the substrate by a control dielectric layer;
- a sidewall spacer overlying the control gate and separated from the structural dielectric layer by a gap;
- an erase gate disposed in the gap and surrounded by an erase dielectric layer;
- and
- a metal bit line contacting the drain region.
6 more elements
Dependencies are inferred from the claim text.