Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration

A double barrier resonant tunneling diode (RTD) integrated with a CMOS/BTJ/SiGe device and circuitry level by means of bonding to form a three-dimensional (3-D) electrically interconnected architecture, comprising:

• a first substrate having substantially horizontal planar upper and lower surfaces, said substrate forming an injection electrode;
• a horizontally layered, patterned RTD formed on the upper surface of said substrate and said RTD having substantially vertical etched lateral edges against which are formed lateral isolation layers;
• and
• a second substrate containing embedded CMOS/BTJ/SiGe devices and circuits, said substrate being bonded to the lower surface of said first substrate and said devices and circuits being electrically connected to said RTD by means of conducting interconnects electrically connected between the RTD and the embedded devices and circuitry.

A method of fabricating a double barrier resonant tunneling diode (RTD) integrated with a CMOS/BJT/SiGe device and circuitry level using metal—metal bonding to form a three-dimensional (3-D) electrically interconnected architecture, comprising:

• providing a substrate having a substantially horizontal planar upper surface, said substrate including an embedded level of CMOS/BJT/SiGe devices and circuitry;
• forming a first metal barrier layer on said planar upper surface;
• forming a first metal bonding layer on said metal barrier layer, said first bonding layer having an exposed surface;
• providing a semiconductor-on-insulator wafer including upper and lower semiconductor layers with an oxide layer formed therebetween;
• reducing the thickness of the upper semiconductor layer by a first etching process to form a quantum well layer;
• forming a lower dielectric tunneling barrier layer on said quantum well layer;
• forming an injection electrode layer on said lower tunneling barrier layer;
• forming a second metal barrier layer on said injection electrode;
• forming a second metal bonding layer on said second metal barrier layer, said second bonding layer having an exposed surface;
• bonding said first and second metal bonding layers at their exposed surfaces, said bonding process also aligning conducting interconnects and vias to said CMOS/BJT/SiGe devices and circuitry;
• reducing the thickness of the lower semiconductor layer by a second etching process;
• removing the lower semiconductor layer by a third etching process;
• removing the substrate oxide layer by a fourth etching process, exposing, thereby, an upper surface of said quantum well layer;
• forming an upper dielectric tunneling barrier layer on said upper surface;
• forming a collection electrode on said upper dielectric tunneling barrier;
• patterning an RTD device of regular horizontal cross-sectional area by a fifth etching process that etches vertically through said collection electrode, said upper tunneling barrier, said quantum well layer and said lower tunneling barrier, said etch stopping at an upper surface of said injection electrode and said etch removing said layers peripheral to said area;
• forming an isolation layer against the vertically etched sides of said RTD device;
• forming electrical contacts to said injection electrode and said collection electrode.

A method of forming a double barrier resonant tunneling diode (RTD) integrated with a CMOS/BJT/SiGe device and circuitry level by means of bonding to form a three-dimensional (3-D) electrically interconnected architecture, comprising:

• providing an SOI wafer first substrate, said substrate including an upper Si layer having an upper surface, a lower Si layer and an oxide layer formed therebetween;
• implanting the upper Si layer with hydrogen to an approximate depth d;
• providing a second Si substrate having a substantially horizontal planar upper surface, said substrate being doped to form an injection electrode;
• forming a first dielectric tunneling barrier layer on said injection electrode, said barrier layer having an upper surface;
• bonding the upper surface of the upper Si layer of the SOI wafer to the upper surface of said barrier layer;
• horizontally cleaving said upper Si layer of the SOI wafer, a portion of approximate thickness d having an exposed upper surface remaining on said barrier layer and the remainder of said SOI wafer being removed;
• smoothing and thinning said upper Si layer portion to form, thereby, a quantum well layer;
• forming a second dielectric tunneling barrier layer on said quantum well layer;
• forming a collection electrode on said second tunneling barrier layer;
• forming a patterned RTD device by etching laterally separated vertical sides through said collection electrode, said upper tunneling barrier layer, said quantum well layer and said lower tunneling barrier layer, said etch stopping at an upper surface of said injection electrode and said etch removing all portions of said layers peripheral to said sides;
• forming an isolation layer against each of the vertically etched sides of said RTD device;
• forming electrical contacts to said injection electrode and said collection electrode.