US 7,001,823 B1 · Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance

Abstract

Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

Claims27

Dependent claims

A method of forming an isolation structure on an integrated circuit substrate, comprising:

etching a trench in the integrated circuit substrate;
forming a lower dielectric layer in the trench, the lower dielectric layer partially filling the trench;
and
forming an upper dielectric layer in the trench over the lower dielectric layer to create an isolation structure;
wherein the upper dielectric layer has an HF etch rate that is approximately equal to or lower than that of Silicon dioxide, and the upper and lower dielectric layers together have an effective dielectric constant that is less than that of silicon dioxide.

2 more elements

Dependencies are inferred from the claim text.

Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance

Life of this patent

Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance

Life of this patent

Abstract

Claims27