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US 6,965,985 B2Granted
Sign generation bypass path to aligner for reducing signed data load latency
AssigneeSun Mirosystems, Inc.
InventorsDavid M. Pini, Yuefei Ge, Anup S. Tirumala
Life of this patent
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Abstract
A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.
Claims9
A method for reducing signed load latency in transfer of data from a cache memory to another element in a microprocessor comprising:
- transferring data from the cache memory to a bypass path and a data path;
- transferring the data to an aligner from the data path;
- generating a sign bit for the data in the bypass path, wherein the generating comprises:
- selecting a plurality of candidate bits from the data, and
- generating the sign bit from the plurality of candidate bits dependent on a select signal, wherein the sign bit is generated independent of propagation of the data through the data path;
- transferring the sign bit to the aligner from the bypass path;
- arranging the data and the sign bit in the aligner into signed data;
- and
- transferring the signed data to the another element.
6 more elements
An apparatus for reducing signed load latency in transfer of data from a cache memory to another element in a microprocessor, comprising:
- a data path connecting the cache memory to an aligner, wherein data is transferred from the cache memory to the aligner via the data path;
- and
- a bypass path connecting the cache memory to the aligner, comprising:
- a sign multiplexer for selecting a plurality of candidate bits from the data in the cache memory;
- and
- a real-sign multiplexer for selecting a sign bit from the plurality of candidate bits dependent on a select signal, wherein the sign bit is selected independent of propagation of data through the data path,
- wherein the sign bit is transferred to the aligner from the bypass path, and
- wherein the aligner arranges the data and the signed bit into signed data and transfers the signed data to the another element.
5 more elements
An apparatus comprising:
- means for transferring data from a cache memory to a bypass path and a data path;
- means for generating a sign bit for the data in the bypass path, wherein the means for generating a sign bit for the data comprises:
- means for selecting a plurality of candidate bits from the data, and
- means for generating the sign bit from the plurality of candidate bits dependent on a select signal,
- wherein the sign bit is generated independent of propagation of data through the data path;
- means for transferring the sign bit to the aligner via the bypass path;
- means for adjusting the data during transfer to the aligner via the data path;
- means for adjusting the sign bit during transfer to the aligner via the bypass path;
- and
- means for selectively processing the part of the data selected for use in generating the sign bit based on an instruction from a CPU;
- means for arranging the data and the sign bit into signed data;
- and
- means for transferring the signed data to another element in a microprocessor.
10 more elements
An apparatus comprising:
- a data path connecting a cache memory to an aligner;
- wherein data is transferred from the cache memory to the aligner along the data path;
- a bypass path connecting the cache memory to the aligner;
- wherein the data is transferred from the cache memory to the bypass path, and
- wherein a sign bit is transferred to the aligner from the bypass path;
- a select component in the bypass path for providing signals to select the sign bit for the data, wherein the select component comprises:
- a sign multiplexer for selecting a plurality of candidate bits from the data;
- and
- a real-sign multiplexer for selecting the sign bit from the plurality of candidate bits,
- wherein the select component provides a signal for selecting a part of the data to generate the sign bit for the data based on an instruction from a CPU;
- wherein the aligner comprises a plurality of sub-aligners;
- and
- wherein the aligner arranges the data and the sign bit into signed data.
10 more elements
Dependencies are inferred from the claim text.