US 6,962,829 B2 · Method of making near chip size integrated circuit package

Abstract

A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

Claims19

Dependent claims

A method of forming a plurality of integrated circuit chip packages, said method comprising:

providing a substrate having a plurality of sections, each of said sections having first metallizations formed on a first surface of said substrate;
coupling an integrated circuit chip to a corresponding one of each of said sections of said substrate;
electrically connecting each said integrated circuit chip to said first metallizations on said corresponding one of said sections;
encapsulating said integrated circuit chips, said first metallizations and said first surface of said substrate with a layer of an encapsulant, wherein said layer of the encapsulant has an outer surface overlying the integrated circuit chips;
placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate on said mounting surface;
cutting said encapsulated substrate while on said mounting surface along a periphery of each of said sections to form said plurality of integrated circuit chip packages.

3 more elements

Dependencies are inferred from the claim text.

Method of making near chip size integrated circuit package

Life of this patent

Method of making near chip size integrated circuit package

Life of this patent

Abstract

Claims19