Early triggered ESD MOSFET protection circuit and method thereof
AssigneeWinbond Electronics Corp.
InventorsShi-Tron Lin, Wei-Fan Chen, Chen-Hsin Lien
Life of this patent
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Abstract
An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 Å and less.
Claims19
An MOSFET ESD protection circuit coupled between a first and a second node, the circuit comprising:
- a first transistor having a drain coupled to the first node and a source coupled to the second node;
- an ESD-transient negative voltage generator receiving an ESD voltage and outputting an ESD-transient negative voltage to a gate of the first transistor to reduce a triggering voltage of the first transistor during an ESD;
- and
- a rectifier receiving and rectifying the ESD-transient negative voltage, and outputting the rectified ESD-transient negative voltage to the gate of the first transistor.
An MOSFET ESD protection circuit coupled between a first and a second node, the circuit comprising:
- a first transistor having a drain coupled to the first node and a source coupled to the second node;
- an ESD-transient negative voltage generator receiving an ESD voltage and outputting an ESD-transient negative voltage to a gate of the first transistor to reduce a triggering voltage of the first transistor during an ESD event;
- and
- a diode coupled between the gate of the first transistor and the second node.
A method for early triggering of an ESD protection circuit for an integrated circuit, the ESD protection circuit having a MOS transistor with a drain coupled to a first node and a source coupled to a second node, the method comprising the step of:
- receiving an ESD voltage and generating an ESD-transient negative voltage;
- and
- rectifying and outputting the ESD-transient negative voltage to a gate of the MOS transistor to reduce a triggering voltage for the MOS transistor to enter snapback when the ESD voltage is applied to the first node.
Dependencies are inferred from the claim text.