Integrated circuit including active components and at least one passive component associated fabrication method

An integrated circuit comprising:

• an onboard memory plane of DRAM cells in a matrix, each of the cells including a control transistor and a storage capacitor;
• a plurality of MOS transistors;
• a first level of interconnection above the storage capacitors;
• a first insulating layer separating the MOS transistors and the base of the storage capacitors;
• and
• a level of local connections including three metal terminals each opening onto each side of the first insulating layer, each of the three metal terminals consisting of a single layer of metal formed within a cavity passing completely through the thickness of the first insulating layer such that the metal terminal passes completely through the thickness of the first insulating layer,
• wherein the first metal terminal forms a first stage of contact between one active area of the integrated circuit and the first level of interconnection, has an upper surface that contacts a second stage of contact between the one active area of the integrated circuit and the first level of interconnection, and extends from the one active area of the integrated circuit to the second stage of contact,
• the second metal terminal vertically connects one active area of the integrated circuit with one plate of one of the storage capacitors, a lower surface of the one plate of the one storage capacitor extending over at least one boundary of an upper surface of the second metal terminal so that a portion of the lower surface of the one plate rests on the upper surface of the second metal terminal and the remainder of the lower surface of the one plate rests on the upper surface of the first insulating layer,
• the third metal terminal horizontally connects two separate active areas of the integrated circuit, and
• the integrated circuit further comprises:
• a second insulating layer above the first insulating layer;
• and
• a cavity passing through the entire thickness of the second insulating layer, the one storage capacitor being set into the cavity.

An information processing system including at least one integrated circuit, the integrated circuit comprising:

• an onboard memory plane of DRAM cells in a matrix, each of the cells including a control transistor and a storage capacitor;
• a plurality of MOS transistors;
• a first level of interconnection above the storage capacitors;
• a first insulating layer separating the MOS transistors and the base of the storage capacitors;
• and
• a level of local connections including three metal terminals each opening onto each side of the first insulating layer, each of the three metal terminals consisting of a single layer of metal formed within a cavity passing completely through the thickness of the first insulating layer such that the metal terminal passes completely through the thickness of the first insulating layer,
• wherein the first metal terminal forms a first stage of contact between one active area of the integrated circuit and the first level of interconnection, has an upper surface that contacts a second stage of contact between the one active area of the integrated circuit and the first level of interconnection, and extends from the one active area of the integrated circuit to the second stage of contact,
• the second metal terminal vertically connects one active area of the integrated circuit with one plate of one of the storage capacitors, a lower surface of the one plate of the one storage capacitor extending over at least one boundary of an upper surface of the second metal terminal so that a portion of the lower surface of the one plate rests on the upper surface of the second metal terminal and the remainder of the lower surface of the one plate rests on the upper surface of the first insulating layer, and
• the third metal terminal horizontally connects two separate active areas of the integrated circuit, and
• the integrated circuit further comprises:
• a second insulating layer above the first insulating layer;
• and
• a cavity passing through the entire thickness of the second insulating layer, the one storage capacitor being set into the cavity.