Method and system for gray-coding counting
AssigneeXilinx, Inc.
InventorsWayson J. Lowe, Eunice Y. D. Hao, Tony K. Ngai, Peter H. Alfke
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Abstract
A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.
Claims12
A system for gray-code counting comprising:
- a binary counter coupled to a reset signal, a clock signal, and a pointer increment signal, and providing a binary output;
- an adder coupled to the binary output and to a selected binary offset value, the adder providing a binary sum output;
- and
- a binary-to-gray converter coupled to the binary sum output and providing a first gray code value representing the binary sum output.
A method for gray-code counting in a programmable logic device comprising steps of:
- adding a selected pointer offset binary value to a pointer count binary value to produce a binary sum;
- converting the binary sum to a gray-code value representing the binary sum;
- providing the gray-code value to a first port of a multiplexer;
- coupling a multiplexer output to a resister input;
- coupling a register output to a second port of the multiplexer;
- and
- incrementing the pointer count binary value in response to a pointer increment signal to create an incremented gray-code value, wherein the incremented gray-code value is selected to be coupled through the multiplexer when a multiplexer select signal is asserted.
A system for gray-code counting in an integrated circuit comprising:
- means for counting a pointer position;
- means for adding an offset value to the pointer position to produce a binary sum;
- and
- means for converting the binary sum to a gray code value;
- means for multiplexing one of the gray code value and an output of a register to an input of the register.
A programmable logic device having a system for gray-code counting comprising:
- a binary counter coupled to a reset signal, a clock signal, and a pointer increment signal, and providing a binary output;
- an adder coupled to the binary output and to a selected binary offset value, the adder providing a binary sum output;
- and
- a binary-to-gray converter coupled to the binary sum output and providing a first gray code value representing the binary sum output.
Dependencies are inferred from the claim text.