Back to results
US 6,894,549 B2Granted
Ferroelectric non-volatile logic elements
AssigneeRamtron International Corporation
InventorJarrod Eliason
Life of this patent
Estimating the term…
Abstract
Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.
Claims97
A ferroelectric, non-volatile SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- and
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and
- wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground;
- and a third ferroelectric capacitor coupled between the Q and complementary Q outputs.
7 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to th Q output;
- and
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and
- wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground, and third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- and
- means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- and
- a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- and
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and
- wherein the first and second NAND gates further comprise an internal drive isolation circuit.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- and
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and
- wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground;
- and a third ferroelectric capacitor coupled between the Q and complementary Q outputs.
7 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- and
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and
- wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground, and third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- and
- means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- and
- a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.
6 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- and
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and
- wherein the first and second NOR gates further comprise an internal drive isolation circuit.
6 more elements
The SR flip-flop of claim 70 further comprising a precharge circuit coupled to the first and second NOR gates.
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first logic gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second logic gate having a first input coupled to the reset input, a second output;
- a ferroelectric capacitor circuit comprising first, second, and third ferroelectric capacitors, including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- a J input;
- a K input;
- a first NAND gate having a first input coupled to the Q output of the SR flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input of the SR flip-flop;
- and
- a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the SR flip-flop and an output coupled to the reset input of the SR flip-flop.
9 more elements
The SR flip-flop of claim further comprising a second controlled power supply coupled to the SR flip-flop.
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first logic gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second logic gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- a J input;
- a K input:
- a first NAND gate having a first input coupled to the Q output of the SR flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input of the SR flip-flop;
- and
- a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the SR flip-flop and an output coupled to the reset input of the SR flip-flop,
- wherein the SR flip-flop further comprises an internal drive isolation circuit.
10 more elements
A ferroelectric, non-volatile, SR flip-flop comprising:
- a set input;
- a reset input;
- a Q output;
- a complementary Q output;
- a first logic gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;
- a second logic gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;
- a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;
- a J input;
- a K input;
- a first NAND gate having a first input coupled to the Q output of the SR flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input of the SR flip-flop;
- a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the SR flip-flop and an output coupled to the reset input of the SR flip-flop;
- and
- a slave JK flip-flop interposed between the Q output and the complementary Q output, and the first input of the first NAND gate and the third input of the second NAND gate.
10 more elements
Dependencies are inferred from the claim text.