Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsAkira Yamaguchi, Muneaki Maeno
Life of this patent
Estimating the term…
Abstract
First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.
Claims32
A semiconductor device comprising:
- a semiconductor substrate;
- a first wiring layer having a first thickness and provided above the semiconductor substrate;
- and
- a second wiring layer having a second thickness thinner than the first thickness and provided above the first wiring layer,
- wherein the first wiring layer comprises a first area having signal lines and a second area having power source lines, and a pitch of the power source lines is greater than that of the signal lines.
A semiconductor device comprising:
- a semiconductor substrate;
- an IP core urea on the semiconductor substrate;
- a peripheral area on the semiconductor substrate except for the IP core area;
- a first wiring layer having a first thickness and provided above the semiconductor substrate in the IP core area;
- and
- a second wiring layer having a second thickness smaller than the first thickness and provided above the first wiring layer in the IP core area,
- wherein the first wiring layer comprises a first area having signal lines and a second area having power source lines, and a pitch of the power source lines is greater than that of the signal lines.
A semiconductor device comprising:
- a semiconductor substrate;
- a first wiring layer having a first thickness and provided above the semiconductor substrate;
- and
- a second wiring layer having a second thickness thinner than the first thickness and provided above the first wiring layer,
- wherein the first wiring layer comprises a first area having signal lines and a second area having power source lines, and a width of each of the power sources lines is greater than that of the signal lines.
A semiconductor device comprising:
- a semiconductor substrate;
- an IP core area on the semiconductor substrate;
- a peripheral end area on the semiconductor substrate except for the IP core area;
- a first wiring layer having a first thickness and provided above the semiconductor substrate in the IP core area;
- and
- a second wiring layer having a second thickness smaller than the first thickness and provided above the first intermediate wiring layer in the IP core area,
- wherein the first wiring layer comprises a first area having signal lines and a second area having power source lines, and a width of each of the power source lines is greater than that of the signal lines.
A semiconductor device comprising:
- a semiconductor substrate;
- a first wiring layer having a first thickness, extending in a direction parallel to a surface of the semiconductor substrate, and provided above the semiconductor substrate;
- a second wiring layer having a second thickness rater than the first thickness, extending in the direction, and provided between the semiconductor substrate and the first wiring layer;
- and
- a third wiring layer having a third thickness greater than the first thickness, extending in the direction, and provided above the first wiring layer;
- wherein the first wiring layer comprises a first area having signal lines and each of the second and third layers comprise a second area having power source lines, and pitch of the power source lines is mater than that of the signal lines.
A semiconductor device comprising:
- a semiconductor substrate;
- a first wiring layer having a first thickness, extending in a direction parallel to a surface of the semiconductor substrate, and provided above the semiconductor substrate;
- a second wiring layer having a second thickness smaller than the first thickness, extending the direction, and provided between the semiconductor substrate and the first wiring layer;
- and
- a third wiring layer having a third thickness smaller than the first thickness, extending in the direction, and provided above the first wiring layer;
- wherein the first wiring layer comprises a first area having signal lines, and each of the second and third layers comprise a second area having signal lines, and a pitch of the power source lines is greater than that of the signal lines.
Dependencies are inferred from the claim text.