US 6,888,201 B2Granted

Bipolar ESD protection structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorTa-Lee Yu

Life of this patent

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Abstract

The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

Claims13

Dependent claims

An integrated multiple vertical npn transistor ESD protection structure on a semiconductor substrate, functionally connected between an integrated circuit input or output pin and ground which will prevent electrostatic discharge damage to said integrated circuit comprising:

a first semiconductor layer having a first conductivity dopant dopent type;
a second semiconductor layer overlying said first semiconductor layer, having a similar conductivity type as said first layer, but a different dopant concentration;
a third semiconductor layer having a second conductivity dopant type opposite that of said first semiconductor layer, disposed in overlying relation to said second semiconductor layer;
a plurality of first regions of said first conductivity type electrically connecting with said first semiconductor layer, having a top element making electrical contact to said first regions and said first semiconductor layer;
a plurality of second regions of said second conductivity dopant type laterally spaced from said first regions, being electrically connected to said third semiconductor layer having a top element making electrical contact to said second regions and said second semiconductor layer;
and
a plurality of third regions of said first semiconductor layer conductivity dopant type laterally spaced and interposed between said second regions,
wherein said third regions form multiple emitter elements, said multiple emitter elements being electrically connected by a conductor element with “N” horizontal stripe conductor elements connected in a contiguous comb like manner by a vertical contact conductor element at one end of said horizontal stripe conductor elements.

5 more elements

An integrated multiple vertical npn transistor ESD protection structure on a semiconductor substrate comprising:

a first semiconductor layer having a first conductivity type with a first dopant concentration;
a second semiconductor layer overlying said first semiconductor layer, said second semiconductor layer having said first conductivity type with a second dopant concentration;
a third semiconductor layer overlying said second semiconductor layer, said third semiconductor layer having a second conductivity type;
a plurality of first regions of said first conductivity type electrically connecting with said first semiconductor layer, having a first top element making electrical contact to said first regions and said first semiconductor layer;
a plurality of second regions of said second conductivity type laterally spaced from said first regions, being electrically connected to said third semiconductor layer having a second top element making electrical contact to said second regions and said second semiconductor layer;
and
a plurality of third regions of said first semiconductor layer conductivity type laterally spaced and interposed between said second regions,
wherein said third regions form multiple emitter elements, said multiple emitter elements being electrically connected by a conductor element with “N” horizontal stripe conductor elements connected in a contiguous comb like manner by a vertical contact conductor element at one end of said horizontal stripe conductor elements.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/790,919Filed 2 Mar 2004 · division
Priority: 9 Aug 2000
Published: US 2004/0169234 A12 Sep 2004
Granted: 3 May 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10D 10/421
Vertical BJTs: having both emitter-base and base-collector junctions ending at the same surface of the body
H10D 89/711
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using bipolar transistors as protective elements
H10D
Inorganic electric semiconductor devices

Family

Application09/635,583Parent of this division · filed 9 Aug 2000
Application10/266,665Parent of this division · filed 8 Oct 2002
US 2004/0169234 A1Pre-grant publication · published 2 Sep 2004
US 6,720,625 B2Parent of this division
US 6,472,286 B1Parent of this division
US 2003/0030116 A1Published application
US 6,888,201 B2This patent

From the US filing history. Foreign family members aren’t listed.