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US 6,887,784 B1Granted
Self aligned metal interconnection and method of making the same
AssigneeCypress Semiconductor Corporation
InventorAlain Blosse
Life of this patent
Estimating the term…
Abstract
A method of making a structure, includes filling a via hole with a conductive material, to form a via. The via hole passes through an etch-stop opening. In both directions along a first axis dielectric material is present between the via hole and edges of the etch-stop layer, and in both directions along a second axis, perpendicular to said first axis, dielectric material is not present between the via hole and edges of the etch-stop layer.
Claims33
A method of making a structure, comprising:
- filling a via hole with a conductive material, to form a via;
- and
- selecting an alignment yield for said semiconductor structure;
- wherein said via hole passes through an etch-stop opening in an etch-stop layer;
- in both directions along a first axis dielectric material is present between said via hole and edges of said etch-stop layer;
- in both directions along a second axis, perpendicular to said first axis, dielectric material is not present between said via hole and edges of said etch-stop layer;
- and
- said via hole has a dimension in the plane of the etch-stop layer smaller than the corresponding etch-stop opening dimension by at least two Lynch values.
5 more elements
A method of making a structure, comprising:
- etching an etch-stop layer, to form an etch-stop opening, wherein said etch-stop layer is on a first dielectric layer;
- depositing a second dielectric layer on said etch-stop layer and in said etch-stop opening;
- etching said first dielectric layer and said second dielectric layer, to form a via hole through said etch-stop opening;
- and
- selecting an alignment yield for said semiconductor structure;
- wherein said via hole passes through said etch-stop opening;
- in both directions along a first axis said second dielectric layer is present between said via hole and edges of said etch-stop layer;
- in both directions along a second axis, perpendicular to said first axis, said second dielectric layer is not present between said via hole and edges of said etch-stop layer;
- and
- said via hole has a dimension in the plane of the etch-stop layer smaller than the corresponding etch-stop opening dimension by at least two Lynch values.
7 more elements
A semiconductor structure, comprising:
- (a) a first dielectric layer,
- (b) an etch-stop layer having an etch-stop opening, on said first dielectric layer,
- (c) a second dielectric layer, on the etch-stop layer, and
- (d) a via, passing through said etch-stop opening,
- wherein said via passes through said etch-stop opening,
- in both directions along a first axis said second dielectric layer is present between said via and edges of said etch-stop layer,
- in both directions along a second axis, perpendicular to said first axis, said second dielectric layer is not present between said via and edges of said etch-stop layer, and
- said via hole has a dimension in the plane of the etch-stop layer smaller than the corresponding etch-stop opening dimension by at least two Lynch values, and said Lynch value is determined from a selected alignment yield.
5 more elements
Dependencies are inferred from the claim text.