Low base-emitter voltage heterojunction bipolar transistor
AssigneeHRL Laboratories, LLC
InventorsDavid Chow, Kenneth Elliott, Chanh Nguyen
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Abstract
A heterojunction bipolar transistor is presented, comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure, and including an emitter layer. The emitter layer includes a strained, n-doped compound of indium arsenic and phosphorus. The transistor further comprises, between the substrate and emitter layer, a subcollector layer, a collector layer, a base layer, and an optional spacer layer. The emitter layer may include a graded portion. A contact layer is formed on the emitter layer to provide contacts for the device.
Claims58
A heterojunction bipolar transistor comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure including an emitter layer including a strained, n-doped compound of indium arsenic and phosphorus.
A method for making a low base-emitter voltage heterojunction bipolar transistor comprising steps of providing a substrate and forming thereon thereon a heterojunction bipolar transistor layer structure lattice-matched to, and including an emitter layer including a strained, n-doped compound a compound of indium arsenic and phosphorus.
Dependencies are inferred from the claim text.