Method of reducing stress migration in integrated circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Ming Huang, Sen-Shan Yang
Life of this patent
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Abstract
A method for reducing stress migration in the copper interconnect line is set forth. In accordance with the method, two anneal steps take place: The first step is at low temperature and of relatively short duration (e.g., about 25-300° C., and about 10 seconds-10 hours). After the first anneal, the wafer is cooled to room temperature. The second step is performed after the cooling step; a higher anneal temperature and longer time duration is needed to enhance performance.
Claims15
A method for reducing stress migration in recessed microstructures of a microelectronic wafer comprising the steps of:
- subjecting the wafer to a first annealing treatment at 25-300° C.;
- cooling the wafer to room temperature;
- and
- subjecting the wafer to a second annealing treatment at 50-400° C.
A method for reducing stress migration in recessed microstructures of a microelectronic wafer comprising the steps of:
- subjecting the wafer to a first annealing treatment at 25-300° C. for from about 10 seconds to about 10 hours;
- cooling the wafer to room temperature;
- and
- subjecting the wafer to a second annealing treatment at 50-400° C.
A method for reducing stress migration in recessed microstructures of a microelectronic wafer comprising the steps of:
- subjecting the wafer to a first annealing treatment at 25-300° C. for from about 10-1000 seconds;
- cooling the wafer to room temperature;
- and
- subjecting the wafer to a second annealing treatment at 50-400° C.
Dependencies are inferred from the claim text.