Method of fabricating a heterojunction bipolar transistor
AssigneesLucent Technologies Inc., Agere Systems Inc.
InventorsRobert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate, Yu-Chi Wang
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Abstract
A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.
Claims17
A method of fabricating a semiconductor device having a semiconductor region, the method comprising the steps of:
- forming at least two conductive posts overlying the semiconductor region by at least a lift-off step to form a structure;
- encapsulating the structure and at least one of the at least two conductive posts to form a planarized cured passivation layer;
- and
- exposing the at least one of the at least two conductive posts protrudingly through the planarized cured passivation layer to form the semiconductor device.
A method of fabricating a semiconductor device having a semiconductor region, the method comprising the steps of:
- forming at least two conductive posts of about the same height by at least a lift-off step overlying the semiconductor region to form a structure;
- encapsulating the structure and the at least two conductive posts to form a planarized cured passivation layer;
- and
- exposing the the at least two conductive posts protrudingly through the planarized cured passivation layer to form the semiconductor device.
A method of fabricating a semiconductor device having a semiconductor region, the method comprising the steps of:
- forming at least one conductive post overlying the semiconductor region to form a structure;
- encapsulating the structure and the at least one conductive post to form a planarized cured passivation layer;
- and
- etching the planarized cured passivation layer causing the encapsulated at least one conductive post to protrude through the planarized cured passivation layer and form the semiconductor device.
Dependencies are inferred from the claim text.