US 6,855,609 B2 · Method of manufacturing ESD protection structure

Abstract

A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Claims8

Dependent claims

A method for manufacturing an electrostatic discharge protection structure comprising the steps of:

providing a semiconductor substrate;
forming a shallow trench opening in the semiconductor substrate
implanting source and drain diffusion regions in the semiconductor substrate;
implanting source and drain wells respectively under the source and drain diffusion regions in the semiconductor substrate;
forming a shallow trench isolation over the semiconductor substrate and in the shallow trench opening in the semiconductor substrate to separate the source and drain diffusion regions and a portion of the source and drain wells;
and
forming source and drain contact structures on the shallow trench isolation respectively over the source and drain diffusion regions and through the shallow trench isolation to contact the source and drain diffusion regions.

4 more elements

A method for manufacturing an electrostatic discharge protection transistor comprising the steps of:

providing a semiconductor p-substrate;
forming a shallow trench opening in the semiconductor p-substrate;
implanting n+ source and n+ drain diffusion regions in the semiconductor p-substrate on both sides of the shallow trench opening;
implanting respective source and drain n-wells under the n+ source and n+ drain diffusion regions in the semiconductor p-substrate;
forming a shallow trench isolation over the semiconductor p-substrate and into the semiconductor p-substrate to separate the n+ source and n+ drain diffusion regions and portions of the source and drain n-wells;
and
forming source and drain contact structures respectively formed on the shallow trench isolation over the n+ source and n+ drain diffusion regions and extending through the shallow trench isolation to contact the n+ source and n+ drain diffusion regions.

4 more elements

Dependencies are inferred from the claim text.

Method of manufacturing ESD protection structure

Life of this patent

Method of manufacturing ESD protection structure

Life of this patent

Abstract

Claims8