Method for forming a box shaped polygate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Shing Chang, Yeur-Luen Tu, Chia-Shiung Tsai, Wen-Ting Chu
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Abstract
A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.
Claims20
A method for forming an improved etching hardmask oxide layer in a polysilicon etching process comprising the steps of:
- providing a planarized semiconductor wafer process surface comprising adjacent first exposed polysilicon portions and exposed oxide portions;
- selectively etching through a thickness portion of the exposed oxide portions;
- thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions;
- exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion;
- and,
- etching through a thickness portion of the second exposed polysilicon portions.
A method for forming an improved self-aligned box-shaped polysilicon word line in an EEPROM memory device comprising the steps of:
- providing a semiconductor wafer comprising a process surface having at least one field effect transistor (FET) device comprising a source line portion including a polysilicon gate electrode and adjacent oxide sidewall spacers;
- blanket depositing an in-situ doped amorphous polysilicon layer over the process surface;
- blanket depositing a silicon nitride layer over the in-situ doped amorphous polysilicon layer according to a PECVD process to avoid crystallization of the in-situ doped amorphous polysilicon layer;
- carrying out a CMP process to expose the polysilicon gate, the oxide sidewall spacers, and a first portion of the in-situ doped amorphous polysilicon layer to respectively form exposed oxide portions and exposed polysilicon portions;
- etching through a thickness portion of the exposed oxide portions;
- and,
- thermally growing a hardmask oxide layer over the exposed polysilicon portions.
Dependencies are inferred from the claim text.