High-speed, current driven latch

A latch circuit having a total current and at least one output, the output having a first distinct state and a second distinct state, the output being controllable by a first trigger signal and a second trigger signal, the latch circuit comprising:

• a first latch transistor;
• a second latch transistor coupled to the first latch transistor;
• a SET transistor coupled to the first latch transistor;
• and
• a RESET transistor coupled to the second latch transistor wherein at least one of the conditions from the group consisting of the following is true:
• 1) at the first state, the total current is conducted by the first latch transistor and the SET transistor wherein the SET transistor switches when the first trigger signal is applied to the SET transistor and 2) at the second state, the total current is conducted by the second latch transistor and the RESET transistor wherein the RESET transistor switches when the second trigger signal is applied to the RESET transistor, and wherein at least one of the conditions from the group consisting of the following is true:
• 1′) the base and emitter of the first latch transistor are coupled to the base and emitter of the SET transistor, respectively, and 2′) the base and emitter of the second latch transistor are coupled to the base and emitter of the RESET transistor, respectively.

A method of changing the output of a latch circuit, the output having a first distinct state and a second distinct state, the latch circuit comprising a first latch transistor, a second latch transistor, a SET transistor and a RESET transistor, the method comprising;

• at the first state, conducting a total current in the first latch transistor and the SET transistor such that the SET transistor is biased at a point close to a first threshold;
• at the second state, conducting the total current in the second latch transistor and the RESET transistor such that the RESET transistor is biased at a point close to a second threshold;
• to vary the output from the first state to the second state, applying a first trigger signal to switch the SET transistor;
• and
• to vary the output from the second state to the first state, applying a second trigger signal to switch the RESET transistor, wherein at least one of the conditions from the group consisting of the following is true:
• 1) the base and emitter of the first latch transistor are coupled to the base and emitter of the SET transistor, respectively, and 2) the base and emitter of the second latch transistor are coupled to the base and emitter of the RESET transistor, respectively.

A method of changing the output of a latch circuit, the output comprising a first distinct state and a second distinct state, the latch circuit comprising a SET circuit and a RESET circuit, the method comprising;

• at the first state, conducting a total current in the SET circuit such that the SET circuit is biased at a point where it will switch the output of the latch based on the introduction to the SET circuit of a first trigger signal;
• and
• at the second state, conducting the total current in the RESET circuit such that the RESET circuit is biased at a point where it will switch the output of the latch based on the introduction to the RESET circuit of a second trigger signal, wherein, the SET circuit includes a first latch transistor and a SET transistor, and the RESET circuit includes a second latch transistor and a RESET transistor, and wherein at least one of the conditions from the group consisting of the following is true:
• 1) the base and emitter of the first latch transistor are coupled to the base and emitter of the SET transistor, respectively, and 2) the base and emitter of the second latch transistor are coupled to the base and emitter of the RESET transistor, respectively.

A latch circuit having an output, the output having a first distinct state and a second distinct state, the output being controllable by a first trigger signal and a second trigger signal, the latch circuit comprising:

• a SET circuit;
• a RESET circuit;
• wherein at least one of the conditions from the group consisting of the following is true:
• 1) at the first state, the SET circuit switches when the first trigger signal is applied to the SET circuit and 2) at the second state, the RESET circuit switches when the second trigger signal is applied to the RESET circuit;
• wherein, the SET circuit includes a first latch transistor and a SET transistor, and the RESET circuit includes a second latch transistor and a RESET transistor;
• and
• wherein at least one of the conditions from the group consisting of the following is true:
• 1′) the base and emitter of the first latch transistor are coupled to the base and emitter of the SET transistor, respectively, and 2′) the base and emitter of the second latch transistor are coupled to the base and emitter of the RESET transistor, respectively.