Method for forming a double-gated semiconductor device

A method for forming a self-aligned double-gated transistor, comprising the steps of:

• depositing an insulative layer over a substrate;
• depositing an amorphous silicon layer over said insulative layer;
• depositing a silicon germanium seed layer in association with said amorphous silicon layer;
• annealing said amorphous silicon layer for recrystallizing said amorphous silicon layer into a polysilicon layer, said polysilicon layer having crystalline structure formations controlled by said silicon germanium seed layer;
• etching said polysilicon layer for defining a source, a drain, and a channel between said source and said drain;
• and
• forming a double-gate electrode over said channel for forming a double-gated transistor, said double-gated electrode having two self-aligned gates.

A method for forming a multi-layer integrated circuit, comprising the steps of:

• forming a first layer integrated circuit and a second layer integrated circuit, said first layer integrated circuit formed between a substrate and said second layer integrated circuit,
• forming said second layer integrated circuit to include a double-gated polysilicon transistor, said double-gated polysilicon transistor formed according to a method comprising the steps of:
• forming an insulative layer for isolating said first layer integrated circuit from said double-gated polysilicon transistor;
• forming an amorphous silicon layer over said insulative layer for yielding a polysilicon layer;
• forming a silicon germanium seed layer associated with said amorphous silicon layer for controlling silicon grain growth in producing said polysilicon layer;
• forming said polysilicon layer using an annealing step applied to said amorphous silicon layer, said annealing step comprising the step of controlling said silicon grain growth using said silicon germanium seed layer;
• and
• forming a source, a drain, and a channel for said double-gated polysilicon transistor from said polysilicon layer, said channel comprising a double-sided vertical fin structure;
• and
• forming a gale in association with said channel and around said double-sided vertical fin structure for forming said double-gated polysilicon transistor.