Layouts for an integrated circuit to perform time and space switching of SONET framed data

A method of laying out an integrated circuit having a first side and a second side opposite each other and a third side and a fourth side opposite each other, the method comprising:

• positioning a first plurality of input/output (I/O) ports along the first side;
• positioning a plurality of queues to be coupled to the first plurality of I/O ports;
• positioning a first bus extending from the plurality of queues toward the second side to couple a control circuit to the plurality of queues;
• positioning second plurality of I/O ports along the third side and the fourth side;
• and
• positioning a second bus between the control circuit and the second plurality of I/O ports to couple the control circuit to the second plurality of I/O ports, wherein the first bus and the second bus are positioned such that the respective bus lines do not cross over each other,
• wherein one or more of the second plurality of I/O ports are laid out comprising:
• positioning a plurality of data lines from the second bus to provide data to the one or more of the second plurality of I/O ports;
• and
• positioning a plurality of cells to be coupled in parallel to each of the plurality of data lines, the plurality of cells to select a predetermined bit in a sequence of data bits received via the plurality of data lines such that data output by the respective I/O ports is output according to a different format than data received via the plurality of data lines,
• wherein each of the plurality of cells is laid out comprising:
• positioning a space control register within the cell, the space control logic to indicate selected data line from the plurality of data lines;
• positioning a multiplexer to be coupled to the space control register, the multiplexer to pass the selected data line;
• positioning a time control register within the cell, the time control register to indicate a selected bit from a sequence of bits received via the selected data line;
• positioning a counter within the cell, the counter to count a number of bits from a predetermined bit in the sequence of bits;
• positioning a comparator to be coupled to the time control register and to the counter, the comparator to generate a load signal in response to the time control register value being equal to the counter value;
• and
• positioning a latch to be coupled to the multiplexer and to the comparator, the latch to latch a value of the selected data line in response to the load signal.