Gate pad protection structure for power semiconductor device and manufacturing method therefor
AssigneePyramis Corporation
InventorsJun Zeng, Ming-Jiang Zhou, Tzong-Shiann Wu
Life of this patent
Estimating the term…
Abstract
A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.
Claims18
A method for manufacturing a gate pad protection structure in an inactive region of a power semiconductor device, the method comprising steps of:
- (a) forming a gate oxide layer on a substrate;
- (b) forming a polysilicon layer on said gate oxide layer;
- (c) simultaneously forming a polysilicon window in an active region of said polysilicon layer and a polysilicon window array in an inactive region of said polysilicon layer;
- and
- (d) performing ion implantations simultaneously via said polysilicon window and said polysilicon window array;
- and
- (e) using an overlapping field implantation area cell array to form said gate pad protection structure in the inactive region of the power semiconductor device.
A gate pad protection structure in an inactive region of a power semiconductor device, the gate pad protection structure comprising:
- a substrate having a gate oxide layer formed on said substrate and a polysilicon layer formed on said gate oxide layer;
- a field implantation area disposed in said substrate;
- an overlapping field implantation area cell array disposed in said substrate and having plural field implantation area cells, each of which substantially has an identical structure to that of said field implantation area, wherein said overlapping field implantation area cell array and said field implantation area are simultaneously formed in said substrate;
- and
- a gate pad structure in an inactive region of the power semiconductor device having a polysilicon window in an active region of said polysilicon layer and a polysilicon window array formed in an inactive region of said polysilicon layer for protecting said gate pad structure by said field implantation area cell array.
A gate pad protection structure in an inactive region of a power semiconductor device, the gate pad protection structure comprising:
- a substrate having a gate oxide layer formed on said substrate and a polysilicon layer formed on said gate oxide layer;
- a field implantation area disposed in said substrate;
- a field implantation area cell array disposed in said substrate and having plural field implantation area cells having a partially overlapping arrangement between adjacent area cells of said plural field implantation area cells, wherein each of said plural field implantation area cells has an identical structure to that of said field implantation area, and wherein said field implantation area cell array and said field implantation area are simultaneously formed in said substrate;
- and
- a gate pad structure in an inactive region of the power semiconductor device having a polysilicon window in an active region of said polysilicon layer and a polysilicon window array formed in an inactive region of said polysilicon layer for protecting said gate pad structure by said field implantation area cell array.
Dependencies are inferred from the claim text.