Digital phase lock loop

A system comprising:

• a system controller;
• a first input for receiving an input reference signal with a first edge;
• and
• a digital phase lock loop, electrically coupled to the system controller and to the first input, comprising:
• an electrical input, electrically coupled to the first input, for receiving the input reference signal;
• an electrical output for providing an output signal that is a digitally generated synthesized version of the input reference signal;
• a control circuit;
• a digital phase detector, electrically coupled to the electrical input, the electrical output, and the control circuit, to compare an edge of the input reference signal to an edge of the output signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the output signal, and wherein the digital phase detector comprises a first delay chain arranged to be driven by the input reference signal and a second delay chain arranged to be driven by the output signal and in opposing timing orientation to the first delay chain, the arrangement of delay elements in the first and second delay chains, respectively, for providing a comparison of the edge of the input reference signal relative to the edge of the output signal;
• and
• a digital frequency synthesizer, being electrically coupled to the control circuit and the digital phase detector, the digital frequency synthesizer comprising:
• a reference clock input for receiving a reference clock signal;
• a digital DLL, electrically coupled to the control circuit and the reference clock input, the digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for the control circuit dynamically configuring the plurality of delay chains for the output signal to achieve a phase lock with an the input reference signal;
• a phase accumulator, electrically coupled to the digital DLL, the digital phase detector, and the control circuit, for precisely dividing a timing period of the input reference signal;
• and
• a non-glitching MUX electrically coupled to the digital DLL, the phase accumulator, and the electrical output, for selecting a tap output from one of the at least one digitally programmable delay element to select glitch-free a first signal comprising at least one pulse from the selected output tap.

A flat panel monitor comprising:

• a controller for controlling functions of the flat panel monitor;
• a display for displaying information;
• a video interface including a first input for receiving an input reference signal with a first edge;
• and
• a digital phase lock loop, electrically coupled to the video interface, the controller, and the display, the digital phase lock loop comprising:
• an electrical input, electrically coupled to the first input, for receiving the input reference signal;
• an electrical output for providing an output signal that is a digitally generated synthesized version of the input reference signal;
• a control circuit:
• a digital phase detector, electrically coupled to the electrical input, the electrical output, and the control circuit, to compare an edge of the input reference signal to an edge of the output signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the output signal, and wherein the digital phase detector comprises a first delay chain arranged to be driven by the input reference signal and a second delay chain arranged to be driven by the output signal and in opposing timing orientation to the first delay chain, the arrangement of delay elements in the first and second delay chains, respectively, for providing a comparison of the edge of the input reference signal relative to the edge of the output signal;
• and
• a digital frequency synthesizer, being electrically coupled to the control circuit and the digital phase detector, the digital frequency synthesizer comprising:
• a reference clock input for receiving a reference clock signal;
• a digital DLL, electrically coupled to the control circuit and the reference clock input, the digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for the control circuit dynamically configuring the plurality of delay chains for the output signal to achieve a phase lock with the input reference signal;
• a phase accumulator, electrically coupled to the digital DLL, the digital phase detector, and the control circuit, for precisely dividing a timing period of the input reference signal;
• and
• a non-glitching MUX electrically coupled to the digital DLL, the phase accumulator, and the electrical output, for selecting a tap output from one of the at least one digitally programmable delay element to select glitch-free a first signal comprising at least one pulse from the selected output tap.