Field effect transistor and image display apparatus using the same
AssigneeHitachi, Ltd.
InventorHajime Akimoto
Life of this patent
Estimating the term…
Abstract
A field effect transistor includes an n+ high-density impurity injection area, a p+ high-density impurity injection area, an i-impurity non-injection area, and a gate electrode. The gate electrode is free from completely lapping over the i-impurity non-injection area, but laps over substantially half the i-impurity non-injection area adjacent to the n+ high-density impurity injection area so as to avoid channel carrier capture levels due to crystal defects/grain boundaries and an effect of potential barriers due to the channel carrier capture levels.
Claims18
An insulated gate field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity type source area thereof, wherein:
- said channel area provides a single channel between said first and second conductivity type source areas and includes a non-overlapped area portion free from being overlapped by the gate electrode in plan, wherein:
- said channel area is comprised of a polycrystal silicon film.
An insulated gate field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity type source area thereof, wherein:
- said channel area provides a single channel between said first and second conductivity type source areas and includes a non-overlapped area portion free from being overlapped by the gate electrode in plan, wherein:
- said channel area is comprised of an intrinsic semiconductor.
An insulated gate field effect transistor having a oate electrode overlapping a channel area between a first conductivity type source area and a second conductivity type source area thereof, wherein:
- said channel area provides a single channel between said first and second source areas and said gate electrode comprises two separate subgate electrodes disposed on respective sides of said first and second conductivity type source areas in a direction in which said channel area extends, wherein:
- said channel area is comprised of an intrinsic semiconductor.
A double field effect transistor device of an insulated gate type, comprising:
- a channel area taking a virtually H-type form in plan;
- a first pair of source areas different in conductivity type from one another respectively formed at opposite ends of one of a pair of parallel strips that comprises a part of the H, wherein a first single channel is provided in said channel area coupling between both of said first pair of source areas;
- a second pair of source areas different in conductivity type from one another respectively formed at opposite ends of the other of said pair of parallel strips that comprises a part of the H so that the source areas formed respectively at the ends of said pair of parallel strips extending in the same direction are different in conductivity type, wherein a second single channel is provided in said channel area coupling between both of said second pair of source areas;
- and
- a gate electrode lapping over an area of the H that comprises the central portions of said pair of parallel strips that comprises a part of the H and a central link of the H that combines said pair of parallel strips.
An image display apparatus comprising a display unit of a plurality of pixels formed on an insulating substrate, and a controller formed on the insulating substrate for at least processing a display signal and for writing the display signal to said display unit, wherein:
- at least part of said controller is comprised of an insulated gate type field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity type source area thereof;
- and
- said channel area includes a non-overlapped area portion free from being overlapped by the gate electrode in plan.
An image display apparatus comprising a display unit of a plurality of pixels formed on an insulating substrate, and a controller formed on the insulating substrate for at least processing a display signal and for writing the display signal to said display unit, wherein:
- at least part of said controller is comprised of an insulated gate type field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity source area thereof;
- and
- said channel area includes a non-overlapped area portion free from being overlapped by the gate electrode in plan;
- and said apparatus comprising:
- an image control unit of said display unit being of an insulated gate type, said image control unit comprising:
- a channel area taking a virtually H-type form;
- a first pair of source areas different in conductivity type from one another respectively formed at opposite ends of one of a pair of parallel strips that comprises a part of the H, wherein a first single channel is provided in said channel area coupling between both of said first pair of source areas;
- a second pair of source areas different in conductivity type from one another respectively formed at opposite ends of the other of said pair of parallel strips that comprises a part of the H so that the source areas formed respectively at the ends of said pair of parallel strips extending in the same direction are different in conductivity type, wherein a second single channel is provided in said channel area coupling between both of said second pair of source areas;
- and
- a gate electrode lapping over an area of the H that comprises the central portions of said pair of parallel strips that comprises a part of the H and a central link of the H that combines said pair of parallel strips.
An insulated gate field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity type source area thereof, wherein:
- said channel area comprises an area portion free from being overlapped by the gate electrode in plan,
- wherein said channel area is comprised of a polycrystal silicon film, and
- wherein the non-overlapped area portion of said channel area has a length longer than a crystal grain size of the polycrystal silicon that comprises said channel area.
An insulated gate type field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity type source area thereof, wherein:
- said gate electrode comprises two separate subgate electrodes disposed on respective sides of said first and second conductivity type source areas in a direction in which said channel area extends, and
- said channel area is comprised of an intrinsic semiconductor.
A double field effect transistor device of an insulated gate type, comprising:
- a channel area taking a virtually H-type form in plan;
- a first pair of source areas different in conductivity type from one another respectively formed at opposite ends of one of a pair of parallel strips that comprises a part of the H;
- a second pair of source areas different in conductivity type from one another respectively formed at opposite ends of the other of said pair of parallel strips that comprises a part of the H so that the source areas formed respectively at the ends of said pair of parallel strips extending in the same direction are different in conductivity type;
- and
- a gate electrode lapping over an area of the H that comprises the central portions of said pair of parallel strips that comprises a part of the H and a central link of the H that combines said pair of parallel strips.
An image display apparatus comprising a display unit of a plurality of pixels formed on an insulating substrate, and a controller formed on the insulating substrate for at least processing a display signal and for writing the display signal to said display unit, wherein:
- at least part of said controller is comprised of an insulated gate type field effect transistor having a gate electrode overlapping a channel area between a first conductivity type source area and a second conductivity source area thereof;
- and
- said channel area includes a non-overlapped area portion free from being overlapped by the gate electrode in plan;
- and said apparatus comprising:
- an image control unit of said display unit being of an insulated gate type, said image control unit comprising:
- a channel area taking a virtually H-type form;
- a first pair of source areas different in conductivity type from one another respectively formed at opposite ends of one of a pair of parallel strips that comprises a part of the H;
- a second pair of source areas different in conductivity type from one another respectively formed at opposite ends of the other of said pair of parallel strips that comprises a part of the H so that the source areas formed respectively at the ends of said pair of parallel strips extending in the same direction are different in conductivity type;
- and
- a gate electrode lapping over an area of the H that comprises the central portions of said pair of parallel strips that comprises a part of the H and a central link of the H that combines said pair of parallel strips.
Dependencies are inferred from the claim text.