Low power differential-to-single-ended converter with good duty cycle performance

A phase-locked loop (PLL) circuit comprising:

• a voltage-controlled oscillator capable of receiving a control voltage and outputting a differential signal having a frequency controlled by said control voltage, said voltage-controlled oscillator comprising a ring oscillator containing a chain of delay cells having differential inputs and differential outputs;
• a differential-to-single-ended (DSE) converter capable of receiving a positive differential input signal and a negative differential input signal from said voltage controlled oscillator and generating a single-ended output signal, said DSE converter comprising:
• a first comparator having a non-inverting input coupled to said positive differential input signal and an inverting input coupled to said negative differential input signal;
• a second comparator having an inverting input coupled to said positive differential input signal and a non-inverting input coupled to said negative differential input signal;
• a first D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of said first comparator;
• a second D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of said second comparator;
• and
• a latch circuit having a first input coupled to an output of said first D flip-flop and a second input coupled to an output of said second D flip-flop, wherein a rising edge on an output of said first D flip-flop causes an output of said latch to change state and a rising edge on an output of said second D flip-flop causes said latch output to change state.