Semiconductor circuit device capable of high speed decoding
AssigneeRenesas Technology Corp.
InventorsNobuyuki Kokubo, Akira Hosogane, Hidemoto Tomita
Life of this patent
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Abstract
An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.
Claims6
A semiconductor circuit device generating an output signal according to a plurality of signals, comprising:
- a plurality of first interconnection lines arranged corresponding to said plurality of signals, respectively;
- a plurality of second interconnection lines arranged corresponding to and in parallel with said plurality of first interconnection lines, each second interconnection line being electrically connected to a corresponding first interconnection line at a prescribed position and transmitting a corresponding signal to the corresponding first interconnection;
- and
- a plurality of logic circuits formed in a lower layer region below the first interconnection lines, each logic circuits receiving a predetermined signal on said plurality of first interconnection lines and logically processing the received signal to generate an output signal.
Dependencies are inferred from the claim text.