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US 6,806,584 B2Granted
Semiconductor device structure including multiple fets having different spacer widths
AssigneeInternational Business Machines Corporation
InventorsKa Hing Fung, Percy V. Gilbert
Life of this patent
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Abstract
A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width.
Claims8
A semiconductor device structure, comprising:
- at least first and second field effect transistors formed on one substrate,
- said first field effect transistor including a first spacer having a first width;
- said second field effect transistor including a second spacer having a second width;
- said first width being different than said second width, wherein said first width has a maximum width in a range of 10 nm to 40 nm, and said second width has a maximum width in a range of 50 nm to 120 nm, so as to increase a drive current performance of said first field effect transistor and to decrease a short channel effect in said second field transistor during a normal operation of said device structure, and
- wherein said structure includes a width transition region located approximately in a middle region between said transistors.
2 more elements
A semiconductor device structure, comprising:
- at least first and second field effect transistors formed on one substrate,
- said first field effect transistor including a first spacer having a first width;
- said second field effect transistor including a second spacer having a second width;
- said first width being different than said second width, wherein said first width has a maximum width in a range of 10 nm to 40 nm, and said second width has a maximum width in a range of 50 nm to 120 nm, so as to increase a drive current performance of said first field effect transistor and to decrease a shown channel effect in said second field transistor during a normal operation of said device structure, and
- wherein said first spacer is I-shaped and said second spacer has an L-shaped part.
2 more elements
A semiconductor device structure, comprising:
- at least first and second field effect transistors formed on one substrate,
- said first field effect transistor including a first spacer having a first width;
- said second field effect transistor including a second spacer having a second width;
- said first width being different than said second width, wherein said first width has a maximum width in a range of 10 nm to 40 nm, and said second width has a maximum width in a range of 50 nm to 120 nm, so as to increase a drive current performance of said first field effect transistor and to decrease a short channel effect in said second field transistor during a normal operation of said device structure, and
- wherein said first spacer is I-shaped.
2 more elements
A semiconductor device structure, comprising:
- at least first and second field effect transistors formed on one substrate,
- said first field effect transistor including a first spacer having a first width;
- said second field effect transistor including a second spacer having a second width;
- said first width being different than said second width, wherein said first width has a maximum width in a range of 10 nm to 40 nm, and said second width has a maximum width in a range of 50 nm to 120 nm, so as to increase a drive current performance of said first field effect transistor and to decrease a short channel effect in said second field transistor during a normal operation of said device structure, and
- wherein said second spacer has an L-shaped part.
2 more elements
A semiconductor device structure, comprising:
- at least first and second field effect transistors formed on one substrate,
- said first field effect transistor including a first spacer having a first width;
- said second field effect transistor including a second spacer having a second width;
- said first width being different than said second width, said first width being different than said second width, wherein said first width has a maximum width in a range of 10 nm to 40 nm, and said second width has a maximum width in a range of 50 nm to 120 nm, so as to increase a drive current performance of said first field effect transistor and to decrease a short channel effect in said second field transistor during normal operation of said device structure, and
- wherein said first field effect transistor has a final suicide to gate spacing (S1) in a range of 10 nm to 20 nm, and said second field effect transistor has a final silicide to gate spacing (S2) in a range of 50 nm to 90 nm.
2 more elements
Dependencies are inferred from the claim text.