PAD arrangement in semiconductor memory device and method of driving semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsMee-Hyun Ahn, Jung-Bae Lee
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Abstract
A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.
Claims11
A semiconductor memory device, comprising:
- a plurality of memory banks;
- and
- a plurality of control pads and a plurality of I/O (input/output) pads for reading data from and writing data in the memory banks, wherein the plurality of control pads and I/O pads are disposed in a region between adjacent memory banks and in a peripheral region surrounding the memory banks.
A semiconductor memory device, comprising:
- a plurality of memory banks arranged at a cell region of a memory chip;
- and
- a plurality of control pads and a plurality of I/O (input/output) pads, separately arranged from each other at the memory chip, for reading data from and writing data in the memory banks, wherein the plurality of control pads are sequentially arranged in a region between adjacent memory banks of the memory chip and the plurality of I/O pads are dispersed in a peripheral region surrounding the memory banks.
A semiconductor memory device, comprising:
- a plurality of memory banks arranged at a cell region of a memory chip;
- and
- a plurality of control pads and a plurality of I/O (input/output) pads for reading data from and writing data in the plurality of memory banks, wherein the plurality of control pads are sequentially arranged in a region between adjacent memory banks and are commonly shared by the plurality of memory banks, and wherein a predetermined number of I/O pads of the plurality of I/O pads are arranged in a periphery region surrounding the memory banks and the plurality of I/O pads are commonly shared by the plurality of memory banks.
A semiconductor memory device, comprising:
- a plurality of memory banks arranged at a cell region of a memory chip, each of the plurality of memory banks comprising a plurality of bank areas;
- a plurality of control pads that are sequentially arranged in a region between adjacent memory banks and are commonly shared by the memory banks;
- and
- a plurality of I/O pads that are arranged in a peripheral region surrounding the memory banks and are commonly shared by memory banks.
A semiconductor memory device, comprising:
- a plurality of memory banks arranged at a cell region of a memory chip;
- and
- a plurality of control pads and a plurality of I/O (input/output) pads for reading data from and writing data in the memory banks,
- wherein each of the plurality of memory banks comprises a plurality of bank areas, wherein the number of bank areas corresponds to the number of the plurality of memory banks and the data corresponding to one of the plurality of bank areas is read from or written in the corresponding bank area of each of the memory banks,
- wherein the plurality of control pads are sequentially arranged in a region between adjacent memory banks and are commonly shared by the plurality of memory banks,
- wherein the plurality of I/O pads are arranged in a peripheral region surrounding the memory banks and are commonly shared by the plurality of memory banks, and
- wherein a predetermined number of I/O pads are allocated to the outer potion of each of the memory banks.
Dependencies are inferred from the claim text.