Fill pattern generation for spin-on glass and related self-planarization deposition

A memory cell comprising:

• a substantially planar semiconductor substrate defining first and second orthogonal in-plane dimensions;
• a switching device disposed over said semiconductor substrate;
• a charge storage device in electrical communication with said switching device;
• a plurality of first topographic structures comprising conductive lead lines deposited over said semiconductor substrate and in electrical communication with said switching device, said topographic structures including a top surface;
• a plurality of second topographic structures with top surfaces thereon, said plurality of second topographic structures comprising the same material as said plurality of first topographic structures and defining first and second in-plane dimensions, and at least one of said fill patterns overlaps with at least one adjacent fill pattern along at least one of said first and second in-plane dimensions, wherein at least a portion of said second topographic structures are T-shaped, said top surfaces of said second topographic structures generally co-planar with said top surfaces of said plurality of first topographic structures;
• at least one geometrically simple array comprising at least a portion of said plurality of first and second topographic structures arranged over said semiconductor substrate such that:
• a substantially continuous straight-edged periphery around said array is defined by said plurality of first topographic structures, second topographic structures or both;
• and
• no portion of said plurality of second topographic structures within said array extends laterally beyond said periphery;
• a gridded valley disposed within said array, said gridded valley comprising a first set of interconnected series of spaces that extend in said first orthogonal in-plane dimension, and a second set of said interconnected series of spaces that extend in said second orthogonal in-plane dimension such that:
• said first and second set of interconnected series of spaces between adjacent ones of said first and second topographic structures define a width of any one of said interconnected series of spaces between 0.25 and 0.5 micron;
• the longest linear dimension of each of said interconnected series of spaces is no longer than the longest dimension of any of said second topographic structures;
• and
• no intersection defined by a crossing between any two of said interconnected series of spaces includes uninterrupted linear dimensions;
• and
• a TEOS planarization layer deposited over said substrate such that it is disposed at least within said gridded valley and laterally surrounds said plurality of first and second topographic structures.

A device comprising a memory cell, wherein said memory cell comprises:

• a substrate with a plurality of peaks and valleys, where said peaks are defined by at least one topographic conductive line spaced apart from a plurality of topographic dummy patterns, and said valleys are defined by interpeak spaces that are formed between said peaks;
• a switching device disposed over said semiconductor substrate;
• a charge storage device in electrical communication with said switching device;
• a repeating array defined by at least a portion of said plurality of peaks and valleys, wherein:
• a substantially continuous straight-edged periphery around said array is defined by said topographic conductive line, dummy patterns or both;
• and
• no portion of any of said plurality of said dummy patterns within said array extends laterally beyond said periphery of said array;
• a grid disposed within said array, said grid defined by said interpeak spaces such that the longest linear dimension of each of said valleys is no longer than the longest lateral dimension of any of said dummy patters, and no intersection defined by a crossing between any two of said interpeak spaces includes uninterrupted linear dimensions;
• and
• a substantially planar layer of insulative material deposited over said valleys, said planar layer having a thickness selected to render a top surface of said substantially planar layer substantially coplanar with a top surface of said peaks.