EEPROM device and method for fabricating same

A method of fabricating an EEPROM memory device, comprising the steps of:

• forming a tunnel insulating layer and a gate insulating layer on a semiconductor substrate on which active regions are defined;
• forming a first conductive layer on the semiconductor substrate on which the tunnel insulating layer and the gate insulating layer are formed;
• patterning the first conductive layer to form first conductive layer patterns, which are separated by cell unit, in a memory transistor, and first conductive layer patterns, which are broken in a word line direction, in a selection transistor;
• forming an insulating layer on the first conductive layer patterns and inactive regions;
• forming a second conductive layer on the insulating layer;
• patterning the second conductive layer to form second conductive layer patterns having contact holes in the selection transistor;
• patterning the second conductive layer patterns to form a sense line of the memory transistor and a word line of the selection transistor;
• forming an interlevel insulating layer having metal contact holes exposing the first conductive layer patterns on the semiconductor substrate;
• and
• forming metal plugs in the metal contact holes to connect the first conductive layer patterns, which are broken in the word line direction, and the second conductive layer patterns by the metal plugs.

A method of fabricating an EEPROM memory device comprising a plurality of memory cells, comprising the steps of:

• depositing a first conductive layer on a semiconductor substrate having active and inactive regions, and patterning the first conductive layer to form floating gates and first wordline portions;
• depositing an insulating layer;
• depositing a second conductive layer and etching the second conductive layer to form first contacts holes in the second conductive layer, and patterning the second conductive layer to form sense line contacts and second wordline portions;
• depositing an interlevel insulating layer and forming second contact holes in the interlevel insulating layer corresponding to the first contact holes in the second conductive layer;
• and
• filling the first and second contact holes with a conductive material to connect the first wordline portions of the first conductive layer and the second wordline portions of the second conductive layer to connect adjacent memory cells to a wordline.