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US 6,806,529 B1Granted
Memory cell with a capacitive structure as a control gate and method of forming the memory cell
AssigneeNational Semiconductor Corporation
InventorsPeter J. Hopper, Yuri Mirgorodski, Andy Strachan
Life of this patent
Estimating the term…
Abstract
In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate, providing a cell with a high overall capacitive coupling ratio, a relatively small area, and a high voltage tolerance.
Claims20
A memory cell comprising:
- a semiconductor material of a first conductivity type;
- spaced apart source and drain regions of a second conductivity type formed in the semiconductor material;
- a channel region located between the source and drain regions;
- a first insulation layer formed over the channel region;
- a first conductive structure formed on the first insulation layer over the channel region;
- an isolation material contacting the first conductive structure;
- and
- a capacitive structure including:
- a plurality of first horizontal sections, the first horizontal sections being conductive;
- a plurality of first vertical sections connected to the plurality of first horizontal sections such that a first vertical section is connected to each first horizontal section, the first vertical sections being conductive and having different vertical dimensions, a first select horizontal section and a first select vertical section connected to the first select horizontal section being electrically connected to the first conductive structure;
- a plurality of second horizontal sections the second horizontal sections being conductive;
- a plurality of second vertical sections connected to the plurality of second horizontal sections such that a second vertical section is connected to each second horizontal section, the second vertical sections being conductive and having different vertical dimensions;
- and
- a plurality of dielectric regions, each dielectric region being connected to a first horizontal section a first vertical section, a second horizontal section, and a second vertical section.
11 more elements
A method of forming a memory cell on a semiconductor material of a first conductivity type, the method comprising the steps of:
- forming spaced apart source and drain regions of a second conductivity type in the semiconductor material, a channel region being located between the source and drain regions;
- forming a first insulation layer over the channel region;
- forming a first conductive structure on the first insulation layer over the channel region;
- forming an isolation material that contacts the first conductive structure;
- forming a first layer of conductive material on a lower horizontal surface and a vertical sidewall surface of an opening to be electrically connected to the first conductive structure;
- forming a first dielectric layer on the first layer of conductive material;
- and
- forming a second layer of conductive material on the first dielectric layer, the second layer of conductive material having a vertical dimension that is shorter than a vertical dimension of the first layer of conductive material.
5 more elements
Dependencies are inferred from the claim text.