US 6,806,510 B2Granted

Semiconductor device with surge protective component and method of manufacturing the semiconductor device

AssigneeShindengen Electric Manufacturing Co., Ltd.

InventorsMinoru Suzuki, Susumu Yoshida

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Abstract

In order to provide a reliable surge protective component with a straightforward manufacturing process, first and second buried layers are diffused over the entire inside surfaces of a semiconductor substrate, and first and second base layers are then diffused over the entire inside surfaces of the first and second buried layers. First and second emitter layers are then partially diffused at the inside of the first and second base layers. The peripheries of the first and second emitter layers are then surrounded by first and second moats, the bottoms of which reach the first and second buried layers. A PN junction formed between the first and second base layers and first and second buried layers is then simply a planar junction.

Claims10

Dependent claims

A semiconductor device manufacturing method comprising, when one of an N-type and P-type is defined as a first conductivity type and the other is defined as a second conductivity type, the steps of:

forming a first buried layer of the first conductivity type in a vicinity of a surface of one side of a semiconductor substrate of the first conductivity type and forming a second buried layer of the first conductivity type in a vicinity of a surface of the other side of the semiconductor substrate, in such a manner that the first and second buried layers sandwich a substrate layer composed of a remaining portion of the semiconductor substrate;
forming first and second base layers of the second conductivity type in a vicinity of surfaces of the first and second buried layers in such a manner that bottom surfaces of said base layers are positioned in the first and second buried layers;
and
forming first and second emitter layers of the first conductivity type in a vicinity of surfaces of the first and second base layers so that bottom surfaces of said emitter layers are positioned in the first and second base layers, wherein
PN junctions formed between the first and second base layers and the first and second buried layers, respectively, are planar junctions.

2 more elements

A semiconductor device comprising, when one of either an N-type or P-type is defined as a first conductivity type and the other is defined as a second conductivity type,

a semiconductor substrate of the first conductivity type,
first and second buried layers of the first conductivity type provided within one side and the other side of the semiconductor substrate respectively, and being of a higher concentration than the semiconductor substrate;
first and second base layers of the second conductivity type provided within a surface of the semiconductor substrate nearer to the surface of the substrate than the first and second buried layers, wherein the first and second buried layers form PN junction to the first and second base layers, respectively;
first and second emitter layers of the first conductivity type, wherein the first and second emitter layers are located in a vicinity of a surface of the first and second base layers so as to form PN junctions with the first and second base layers, respectively,
first and second ohmic layers of the second conductivity type and being of a higher concentration than the first and second base layers, wherein the first and second ohmic layers are located in a vicinity of a surface of the first and second base layers,
a ring-shaped first moat positioned at an edge portion of regions constituted by the first emitter layer and first ohmic layer, wherein the first moat has a bottom surface deeper than the first base layer and the bottom surface reaches the first buried layer,
and a ring-shaped second moat positioned at an edge portion of regions constituted by the second emitter layer and second ohmic layer, wherein the second moat has a bottom surface deeper than the second base layer and the bottom surface reaches the first buried layer,
wherein the first and second base layers are exposed at a side surface of the first and second moats so as to form planar PN junctions between the first and second base layers and the first and second emitter layers.

5 more elements

Dependencies are inferred from the claim text.