Semiconductor device capable of preventing ring defect and method of manufacturing the same

A semiconductor device comprising:

• a semiconductor substrate having a junction region;
• a planarization layer formed on the substrate and having an interface with the substrate, the planarization layer having a first contact hole portion through which the junction region is exposed;
• an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer, the interlayer dielectric layer having a second contact hole portion extended from the first contact hole portion;
• and
• contact spacers formed at sidewalls of the first and second contact hole portions,
• wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate,
• wherein the interlayer dielectric layer has a slower etching rate than the planarization layer in an etchant used to form the first and second contact hole portions, and the contact spacers are formed of a material having a slower etching rate than the interlayer dielectric layer and the planarization layer in a cleaning solution, and
• wherein the junction region includes a groove through which the interface between the planarization layer and the semiconductor substrate is exposed.

A method of manufacturing a semiconductor device comprising:

• providing a semiconductor substrate having a junction region;
• sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate, producing a first interface between the planarization layer and the substrate and a second interface between the planarization layer and the interlayer dielectric layer;
• forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer;
• forming a trench in the exposed junction region of the semiconductor substrate;
• forming contact spacers at the sidewalls of the contact hole, the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region;
• cleaning the surface of the semiconductor substrate;
• and
• forming a conductive line to contact the exposed junction region,
• wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.