Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process

A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, said method comprising:

• providing a semiconductor substrate with a first conductive type;
• forming a plurality of shallow trench isolations in said substrate;
• forming a first well with a second conductive type between one pair of said shallow trench isolations in said substrate;
• forming a dummy gate above said first well on said substrate;
• forming a MOS-like gate with said second conductive type on said substrate beside said first well;
• forming first highly doped diffusion regions with said second conductive type beside each side of said MOS-like gate in said substrate, one of said first diffusion regions across one portion of said first well and one portion of said substrate and adjacent to one side of said dummy gate, while another one of said first diffusion regions from opposite to said one of said first diffusion regions connected to a cathode terminal;
• and
• forming a second highly doped diffusion region with said first conductive type beside said dummy gate, said second highly doped diffusion region formed opposite to said one of said first diffusion regions and adjacent to said dummy gate, said second diffusion region connected to an anode terminal.