Method for fabricating semiconductor device with triple well structure
AssigneeHynix Semiconductor Inc.
InventorJae-Geun Oh
Life of this patent
Estimating the term…
Abstract
A method for fabricating a triple well in a semiconductor device, includes the steps of forming a first well of a first conductive type with a first concentration lower than a first target concentration, wherein the first concentration is the minimum dose capable of isolating neighboring wells each other and forming a second well of a second conductive type with a second concentration higher than a second target concentration, wherein the second well includes a first region surrounded by the first well and a second region isolated from the first region by the first well.
Claims20
A method for fabricating a triple well in a semiconductor device, comprising the steps of:
- forming a first well of a first conductive type with a first concentration by a first ion-implantation process, wherein the first concentration is the minimum dose capable of isolating neighboring wells each other;
- and
- forming a second well of a second conductive type with a second concentration by a second ion-implantation process, wherein the second well includes a first region surrounded by the first well and a second region isolated from the first region by the first well,
- wherein the first ion-implantation process is performed to form a third region by implanting impurities with a dose of about 5×1012 ions/cm2 to about 1.5×1013 ions/cm2 and with an ion-implantation energy of about 0.6 MeV to about 1.6 MeV.
A method forming a semiconductor device, comprising steps of:
- forming a first well of a first conductive type with a first concentration by a first ion-implantation process in a semiconductor substrate, wherein the first concentration is the minimum dose capable of isolating neighboring wells each other;
- forming a second well of a second conductive type with a second concentration, the second well surrounded by the first well;
- implanting impurities of the second conductive type to adjust a threshold voltage of a transistor to be formed on a surface of the semiconductor substrate;
- forming a gate oxide layer and a gate electrode on a predetermined region on the second well;
- and
- forming source/drain regions with a first conductive type at both sides of the gate electrode in the second well,
- wherein the first ion-implantation process is performed to form a third region with a does of about 5×1012 ions/cm2 to about 1.5×1013 ions/cm2 and with an ion-implantation energy of about 0.6 MeV to about 1.6 MeV.
A method for fabricating a triple well in a semiconductor substrate, comprising the steps of:
- forming a first region by implanting impurities of a first conductive type with a dose of about 5×1012 ions/cm2 to about 1.5×1013 ions/cm2 and an ion-implantation energy of 0.6 MeV to about 1.6 MeV;
- forming a second region by implanting impurities of the first conductive type with a dose of about 5×1012 ions/cm2 to about 2×1013 ions/cm2 and an ion-implantation energy of 500 KeV to about 600 KeV;
- forming a first field stop region of a second conductive type with a dose of 5×1011 ions/cm2 to about 2×1013 ions/cm2 and an ion-implantation energy of about 150 KeV to about 300 KeV between the second region and the surface of the semiconductor substrate;
- forming a third region by implanting impurities of the second conductive type with a dose of about 5×1012 ions/cm2 to about 3×1013 ions/cm2 and an ion-implantation energy of about 180 KeV to about 300 KeV between the first region and the surface of the semiconductor substrate, the third region includes a fourth region and a fifth region isolated each other by the second region;
- and
- forming a second field stop region of the first conductive type with a dose of 5×1011 ions/cm2 to about 1×1013 ions/cm2 and an ion-implantation energy of about 50 KeV to about 80 KeV.
Dependencies are inferred from the claim text.